San Jose State University Department of Electrical Engineering Dec 5th, Fall 2005 EE 166 PROJECT Advisor: Prof. David Parent Group Members Radhika Arora,

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Presentation transcript:

San Jose State University Department of Electrical Engineering Dec 5th, Fall 2005 EE 166 PROJECT Advisor: Prof. David Parent Group Members Radhika Arora, Nupur Sinha, Meeta Jayaswal 16-BIT CARRY LOOK AHEAD ADDER

Presentation Overview  Abstract  Introduction and Design Principle  Theory of Operation  Design Flow and Longest Path Calculation  Specifications  Project Schematic, Layout and Verification  Cost Analysis  Applications  Project Summary  Conclusion  Acknowledgement

Abstract Successfully designed a 16-bit Carry Look Ahead Adder by using Cadence CAD tools. The entire project is designed towards AMI06 process specification. The design has successfully passed DRC and LVS, as well as met the desired 200MHz clock speed, power and area constraints.

Introduction Carry Look Ahead Adder are the building blocks for other logics such as MSI adders and ALU. It is faster compared to ripple carry logic adders or full adders especially when adding a large number of bits. The Carry Look Ahead Adder is able to generate carries before the sum is produced using the propagate and generate logic to make addition much faster.

Design Principle Block of DFFs Carry Propagate and Generate Block Carry Look Ahead Logic Sum Generator

Theory of operation Carry values calculated independently (determines carry ahead of time) Propagate and Generate terms: Gi = Ai + Bi and Pi = Ai XOR Bi Then outputs can be summarized as, Sum:Si=Pi xor Ci Carry:Ci+1=Gi +PiCi C0:Previous carry C1 = G0 + P0C0 C2 = G1+P1G0+P1P0C0 C3=G2+P2G1+P2P1G0+P2P1P0C0 C4=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0C0

4-Bit Carry Look Ahead Adder Gate Level Design P G

Design Flow Functions and Specs Designing For Logic Hand Calculations Initial Sizing Stick Diagrams Layout DRC & Extraction LVS Post Extraction

Specifications Speed: 200MHz Area: 969 X 375 um Rising time and Falling time: 5 ns Capable load: 35 fF Propagation Delay: 0.5 ns

Final Schematic

Final Schematic-General View

Final Simulation A=0011 B=0100 Cin= Test Vectors

Final Simulation

Final Layout

LVS Verification Net-lists match!

Applications Most widely used design for high speed adders. It is used - For explicit arithmetic operations. - For computing physical addresses in most modern CPUs. - Used in digital systems where full fledged CPUs are superfluous. Speed of various digital systems is significantly influenced by speed of adders.

Cost Analysis 1.Cadence software available at SJSU. 2.Total cost: $0.00 & 200 working hrs.

Project Summary We used the gate design methodology instead the AOI design method for Carry logic because of its lesser drain capacitance. We were able to meet timing specifications and it also made hand calculations easier to do. We used a less complicated design and created separate cells in order make debugging easier and also allow for a neater layout.

Conclusion  What has been achieved?  Area: 969 X 375 um  Propagating Time: 0.4 ns  Rising time and Falling time: 5 ns  Capable load: 35 fF  Power: 47mW

Acknowledgements Thanks to Cadence Design Systems for the VLSI lab Thanks to Synopsys for software donation. Professor David Parent for guiding us for success! Undo, Stretch, Copy, Move!