CS 140 Lecture 3 Professor CK Cheng 10/3/02. 1.Specification 2.Implementation 3.K-maps Part I.

Slides:



Advertisements
Similar presentations
Techniques for Combinational Logic Optimization
Advertisements

1 CK Cheng CSE Dept. UC San Diego CS 140, Lecture 2 Combinational Logic.
Combinational Logic Circuits Is the logic circuit where the output always depends on the inputs irrespective of the previous state with out the feed back.
ECE 301 – Digital Electronics Karnaugh Maps (Lecture #7) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,
ECE 301 – Digital Electronics Minterm and Maxterm Expansions and Incompletely Specified Functions (Lecture #6) The slides included herein were taken from.
ECE 331 – Digital System Design
ENGIN112 L8: Minimization with Karnaugh Maps September 19, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 8 Minimization with Karnaugh.
CS 140 Lecture 5 Professor CK Cheng 10/10/02. Part I. Combinational Logic 1.Spec 2.Implementation K-map: Sum of products Product of sums.
CS 140 Lecture 2 Combinational Logic CK Cheng 4/04/02.
1 CS 140 Lecture 3 Combinational Logic Professor CK Cheng CSE Dept. UC San Diego.
1 CS 20 Lecture 14 Karnaugh Maps Professor CK Cheng CSE Dept. UC San Diego.
CS 140 Lecture 3 Professor CK Cheng Tuesday 4/09/02.
1 CK Cheng CSE Dept. UC San Diego CS 140, Lecture 2 Combinational Logic.
CS 140 Lecture 6: Other Types of Gates Professor CK Cheng 1.
CS 140 Lecture 4 Professor CK Cheng Tuesday 5/08/02.
CS 140 Lecture 6 Professor CK Cheng Tuesday 10/15/02.
CS 140 Lecture 4 Combinational Logic: K-Map Professor CK Cheng CSE Dept. UC San Diego 1.
Lecture 1: Introduction to Digital Logic Design CK Cheng Tuesday 4/1/02.
1 CS 140 Lecture 3 Combinational Logic Professor CK Cheng CSE Dept. UC San Diego.
Design of Two-Level Multiple-Output Networks
CS 140 Lecture 6 Professor CK Cheng UC San Diego.
CS 140 Lecture 4 Professor CK Cheng 4/11/02. Part I. Combinational Logic Implementation K-Map Given F R D Obj: Minimize sum of products Proc: Draw K-Map.
ECE 331 – Digital System Design Karnaugh Maps and Determining a Minimal Cover (Lecture #7) The slides included herein were taken from the materials accompanying.
ECE 301 – Digital Electronics Karnaugh Maps and Determining a Minimal Cover (Lecture #8) The slides included herein were taken from the materials accompanying.
CS 151 Digital Systems Design Lecture 8 Minimization with Karnaugh Maps.
CS 140 Lecture 5 Professor CK Cheng CSE Dept. UC San Diego.
CS 140 Lecture 5 Professor CK Cheng CSE Dept. UC San Diego 1.
CS 140 Lecture 7 Professor CK Cheng 10/17/02. Combinational Logic  Complete set of gates  Other types of gates 1)XOR 2)NAND / NOR 3)Block Diagram Transfers.
Simplifying Boolean Expressions Using K-Map Method
1 CK Cheng CSE Dept. UC San Diego CSE 140, Lecture 2 Combinational Logic.
Lecture 3: Incompletely Specified Functions and K Maps CSE 140: Components and Design Techniques for Digital Systems Fall 2014 CK Cheng Dept. of Computer.
Logic Function Optimization. Combinational Logic Circuit Regular SOP and POS designs Do not care expressions Digital logic circuit applications Karnaugh.
BOOLEAN ALGEBRA Saras M. Srivastava PGT (Computer Science)
ECE 331 – Digital System Design
K-map Dr. Bernard Chen Ph.D. University of Central Arkansas Spring 2009.
1 Simplification of Boolean Functions:  An implementation of a Boolean Function requires the use of logic gates.  A smaller number of gates, with each.
Module 9.  Digital logic circuits can be categorized based on the nature of their inputs either: Combinational logic circuit It consists of logic gates.
07 KM Page 1 ECEn/CS 224 Karnaugh Maps. 07 KM Page 2 ECEn/CS 224 What are Karnaugh Maps? A simpler way to handle most (but not all) jobs of manipulating.
LOGIC GATES & BOOLEAN ALGEBRA
Simplification of switching functions Simplify – why? –Switching functions map to switching circuits –Simpler function  simpler circuit –Reduce hardware.
Ahmad Almulhem, KFUPM 2010 COE 202: Digital Logic Design Combinational Logic Part 3 Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
XOR Operator A short digression… … to introduce another Boolean operation: exclusive- OR (XOR) ABA + B XOR.
CS151 Introduction to Digital Design Chapter Map Simplification.
Copied with Permission from prof. Mark PSU ECE
BR 2/1/991 Truth Tables (again) Recall that a boolean equation can be represented by a Truth Table A B C F
Karnaugh Maps Not in textbook. Karnaugh Maps K-maps provide a simple approach to reducing Boolean expressions from a input-output table. The output from.
1 CK Cheng CSE Dept. UC San Diego CSE 140, Lecture 2 Combinational Logic.
CSE 140: Components and Design Techniques for Digital Systems Lecture 3: Incompletely Specified Functions and K Maps CK Cheng Dept. of Computer Science.
CEC 220 Digital Circuit Design More Karnaugh Maps Monday, February 02 CEC 220 Digital Circuit Design Slide 1 of 11.
Review. Boolean Algebra.
K-map Dr. Bernard Chen Ph.D. University of Central Arkansas Spring 2009.
ECE DIGITAL LOGIC LECTURE 8: BOOLEAN FUNCTIONS Assistant Prof. Fareena Saqib Florida Institute of Technology Spring 2016, 02/11/2016.
ECE 301 – Digital Electronics Minimizing Boolean Expressions using K-maps, The Minimal Cover, and Incompletely Specified Boolean Functions (Lecture #6)
Based on slides by:Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. ECE/CS 352: Digital System Fundamentals Lecture 7 – Karnaugh Maps.
Lecture 5: K-Map minimization in larger input dimensions and K-map minimization using max terms CSE 140: Components and Design Techniques for Digital Systems.
Logic Gates, Boolean Algebra and Karnaugh Maps. Challenge! By the end of todays session can you complete the following?
1 EENG 2710 Chapter 3 Simplification of Switching Functions.
Digital Logic & Design Dr. Waseem Ikram Lecture 09.
Lecture 3: Incompletely Specified Functions and K Maps
Karnaugh Maps.
Lecture 3: Incompletely Specified Functions and K Maps
CHAPTER 5 KARNAUGH MAPS 5.1 Minimum Forms of Switching Functions
CSE 140: Components and Design Techniques for Digital Systems
ECE 331 – Digital System Design
Combinatorial Logic Circuit
CSE 20 Lecture 9 Boolean Algebra: Theorems and Transformations
CSE 140 Lecture 3 Combinational Logic: Implementation
Professor CK Cheng CSE Dept. UC San Diego
CSE 140 Lecture 4 Combinational Logic: K-Map
Lecture 3: Incompletely Specified Functions and K Maps
Presentation transcript:

CS 140 Lecture 3 Professor CK Cheng 10/3/02

1.Specification 2.Implementation 3.K-maps Part I.

Literals x i or x i ’ Product Termx2x1’x0 Sum Termx2 + x1’ + x0 Minterm of n variables: A product of n variables in which every variable appears exactly once. Definitions

Implementation Spec  Schematic Diagram Net list Obj min cost Switching expression (max performance) Cost: wires, gates  Variables, product terms, sum terms We want to minimize # of terms, # of literals

Implementation (Optimization) Id a b f (a, b) a’b ab’ ab Karnaugh map – 2D truth table

Function can be represented by sum of minterms: f(a,b) = a’b + ab’ + ab This is not optimal however! We want to minimize the number of literals and terms. We factor out common terms – a’b + ab’ + ab = a’b + ab’ + ab + ab = (a’+a)b + a(b’+b) = b + a f(a,b) = a + b

On the K-map however: b = 0 b = 1 a = 0 a = a’b ab’ ab f(a,b) = a + b

Another example Id a b f (a, b) a’b ab f(a,b) = a’b + ab = (a’ + a)b = b

On the K-map: b = 0 b = 1 a = 0 a = ab’ ab f(a,b) = b

Using Minterms Id a b f (a, b) a + b a ‘ + b f(a,b) = (a + b)(a’ + b) = b + aa’ = b + 0 = b

Two variable K-maps Id a b f (a, b) f (0, 0) f (0, 1) f (1, 0) f (1, 1) 2 variables means we have 2 2 entries and thus we have 2 to the 2 2 possible functions for 2 bits, which is 16. f(a,b) abab

Three variables K-maps Id a b c f (a,b,c,d)

Corresponding K-map c = 1 a = 1 b = (0,0) (0,1) (1,0) (1,0) a = 0 Gray code f(a,b,c) = a’

Another example Id a b c f (a,b,c,d)

Corresponding K-map c = 1 a = 1 b = (0,0) (0,1) (1,0) (1,0) a = 0 f(a,b,c) = b + ca’

Yet another example Id a b c f (a,b,c,d)

Corresponding K-map c = 1 a = 1 b = (0,0) (0,1) (1,0) (1,0) a = 0 f(a,b,c) = c’