Enigma Machine - Design Presentation Group M1 Adithya Attawar Shilpi Chakrabarti Zavo Gabriel Michael Sokolsky Digital World War II Enigma Cipher Wed.

Slides:



Advertisements
Similar presentations
Programmable FIR Filter Design
Advertisements

Reliable Data Processor in VLSI
Give qualifications of instructors: DAP
EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 5 Programmable.
1 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Programmable Configurations Read Only Memory (ROM) – –a fixed array of AND gates.
1 Codes, Ciphers, and Cryptography-Ch 3.2 Michael A. Karls Ball State University.
Team Name: team13 Programmer: 陳則凱 b Tester: 劉典恆 b
Symmetric Encryption Example: DES Weichao Wang. 2 Overview of the DES A block cipher: – encrypts blocks of 64 bits using a 64 bit key – outputs 64 bits.
Enigma? Several Images from Wikipedia (an online encyclopedia)
Enigma Meghan Emilio Faculty Sponsor: Ralph Morelli (Computer Science)
CPEN Digital System Design
CS 151 Digital Systems Design Lecture 37 Register Transfer Level
[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Nov. 19 Overall Project Objective : Dynamic Control.
Team M1 Enigma Machine Milestone March, 2006 Design Manager: Prateek Goenka Adithya Attawar (M11) Shilpi Chakrabarti (M12) Mike Sokolsky (M14) Design.
David Reed Department of Computer Science Creighton University Nifty Assignments: Encryption & the Enigma Machine.
Team M1 Enigma Machine Milestone 5 Adithya Attawar (M11) Shilpi Chakrabarti (M12) Zavo Gabriel (M13) Mike Sokolsky (M14) Design Manager: Prateek Goenka.
[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 22 Overall Project Objective : Dynamic Control.
1 Team M1 Enigma Machine 3rd May, 2006 Adithya Attawar (M11) Shilpi Chakrabarti (M12) Mike Sokolsky (M14) Design Manager: Prateek Goenka Adithya Attawar.
1 Overview of the DES A block cipher: –encrypts blocks of 64 bits using a 64 bit key –outputs 64 bits of ciphertext A product cipher –basic unit is the.
[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 27 Overall Project Objective : Dynamic Control.
E-Voting Machine - Design Presentation Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober Mon. Sept 29 System Hardware Component Diagram.
1 Team M1 Enigma Machine Milestone March, 2006 Adithya Attawar (M11) Shilpi Chakrabarti (M12) Zavo Gabriel (M13) Mike Sokolsky (M14) Design Manager:
1 Team M1 Enigma Machine Milestone March, 2006 Adithya Attawar (M11) Shilpi Chakrabarti (M12) Zavo Gabriel (M13) Mike Sokolsky (M14) Design Manager:
Team W3: Anthony Marchetta Derek Ritchea David Roderick Adam Stoler Milestone 9: March 31st Chip Level Simulatio Overall Project Objective: Design an Air-Fuel.
1 Team M1 Enigma Machine Milestone April, 2006 Adithya Attawar (M11) Shilpi Chakrabarti (M12) Mike Sokolsky (M14) Design Manager: Prateek Goenka.
Team M1 Enigma Machine Adithya Attawar (M1-1) Shilpi Chakrabarti (M1-2) Zaven Gabriel (M1-3) Michael Sokolsky (M1-4) Design Manager: Prateek Goenka Week.
Team LIT Scott Butler Kristin Haeusler Michael Hatt Brock Smith.
Recap – Our First Computer WR System Bus 8 ALU Carry output A B S C OUT F 8 8 To registers’ input/output and clock inputs Sequence of control signal combinations.
Team M1 Enigma Machine Milestone April, 2006 Design Manager: Prateek Goenka Adithya Attawar (M11) Shilpi Chakrabarti (M12) Mike Sokolsky (M14) Design.
Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage II: 26 th January 2004.
Enigma Meghan Emilio Advisor: Professor Ralph Morelli April 2004.
Data Representation (in computer system) Computer Fundamental CIM2460 Bavy LI.
Random Number Generator Dimtriy Solmonov W1-1 David Levitt W1-2 Jesse Guss W1-3 Sirisha Pillalamarri W1-4 Matt Russo W1-5 Design Manager – Thiago Hersan.
E-Voting Machine - Design Presentation Group M1 Jessica Kim Chi Ho Yoon Jonathan Chiang Donald Cober Mon. Sept 8 Initial Design Secure Electronic Voting.
Block and Stream Ciphers1 Reference –Matt Bishop, Computer Security, Addison Wesley, 2003.
Figure to-1 Multiplexer and Switch Analog
Dan Boneh Introduction History Online Cryptography Course Dan Boneh.
Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Lecture 12 – Design Procedure.
Chapter 5 Memory and Programmable Logic 5.1. Introduction 5.2. Random Access Memory 5.3. Memory Encoding 5.4. Read Only Memory 5.5. Programmable Logic.
Unit 9 Multiplexers, Decoders, and Programmable Logic Devices
Team Name: team13 Programmer: 陳則凱 b Tester: 劉典恆 b
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Xilinx Design Flow FPGA Design Flow Workshop.
Day 18. Concepts Plaintext: the original message Ciphertext: the transformed message Encryption: transformation of plaintext into ciphertext Decryption:
1/8/ L20 Project Step 8 - Data Path Copyright Joanne DeGroat, ECE, OSU1 State Machine Design with an HDL A methodology that works for documenting.
Dan Boneh Symmetric Encryption History Crypto. Dan Boneh History David Kahn, “The code breakers” (1996)
6.375 Final Presentation Jeff Simpson, Jingwen Ouyang, Kyle Fritz FPGA Implementation of Whirlpool and FSB Hash Algorithms.
This material exempt per Department of Commerce license exception TSU Xilinx Tool Flow.
Programmable Logic Training Course HDL Editor
TAP Controller for Cell-Based Design Myrna Bussiere, Project Leader Meagan Morrell.
Encryption of WWII Philip Gebhardt 10/24/2011. Interest.
Group M1 - Enigma Machine Design Manager: Prateek Goenka Adithya Attawar (M1-1) Shilpi Chakrabarti (M1-2) Zavo Gabriel (M1-3) Mike Sokolsky (M1-4) Milestone.
ELEE 4303 Digital II Introduction to Verilog. ELEE 4303 Digital II Learning Objectives Get familiar with background of HDLs Basic concepts of Verilog.
Introduction ProjectRequirements Project Requirements In a previous senior design project, a wireless front-end was added to Iowa State University’s Teradyne.
1 ENGG 1015 Tutorial Three Examples of Finite State Machines Supplementary notes Learning Objectives  Learn about Design of Finite State Machines Ack.:
1 CS 151: Digital Design Chapter 3: Combinational Logic Design 3-1Design Procedure CS 151: Digital Design.
Computer Security coursework 3 Dr Alexei Vernitski.
The Enigma Machine Eric Roberts CS 106A February 3, 2016.
By, Amanda Rydzynski O’Brien Computer Skills
University of Malawi, Chancellor College
Random Logic l Forum.NET l State Machine Mechanism Forum.NET 1 st Meeting ● December 27, 2005.
State Machine Design State Machine Design Digital Electronics
Automatic Guitar Tuner Group #10 Dariusz Prokopczak & Stephan Erickson ECE 445 Sr. Design December 9, 2014.
C OMBINATIONAL L OGIC D ESIGN 1 Eng.Maha AlGubali.
FIGURES FOR CHAPTER 16 SEQUENTIAL CIRCUIT DESIGN
A computer consists of five functionally independent main parts.
Introduction to the FPGA and Labs
Rotor Ciphers.
Lecture 8 Logistics Last lecture Last last lecture Today
Lecture 9 Logistics Last lecture Last last lecture Today
WORLD OF WONDERS : THE ENIGMA MACHINE
Presentation transcript:

Enigma Machine - Design Presentation Group M1 Adithya Attawar Shilpi Chakrabarti Zavo Gabriel Michael Sokolsky Digital World War II Enigma Cipher Wed. Jan 25 Initial Design

Status  Finished:  Design selections  Block diagram for processes  To Do:  Verilog  Schematic  Layout  Testing  Simulation

Design Decisions  Project Overview  Implement on chip the functionality of a World War II Enigma cipher machine.  A sophisticated variation on a simple substitution code, it involves a string of 9 letter pair substitutions, some of which change for each new character sent through it.  Must re-create the effect of both the electrical and mechanical aspects of the device on chip.  User must be able to change the configuration.  We will represent each character as a 5-bit number.

Design Decisions cont.  Project Overview  Initial settings are:  8 Possible wheels (4 bits)  3 Wheels (15 bits)  Plugboard (12 bits)  Signal travels through plugboard, 3 wheels, reflector, back through 3 wheels, back through plugboard, illuminates encoded letter.  Historically significant code, breaking it had a significant impact on WWII

Block Overview

Block Functions  Logic Array trans.  Emulates pegboard to swap characters, fundamentally a programmable FSM  Direction Select trans.  Routes the character through 3 of the 8 wheels in the correct order, then through the Reflector, back through the wheels, and then back to the Logic Array  Wheel Logic trans.  Takes input character and wheel position and outputs a swapped character  Reflector/Registers trans.  Performs a fixed character swap and holds the result for the next cycle, to pass back through all of the previous logic

Questions? Adding more encryption options? The ability to have A->A Automatic key generation? Randomized wheel movement?