UC Berkeley, Dept of EECS EE141, Fall 2005, Project 2 Speed-Area Optimized 8-Bit Adder Presentation Slides.

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UC Berkeley, Dept of EECS EE141, Fall 2005, Project 2 Speed-Area Optimized 8-Bit Adder Presentation Slides

EE141 – Project 22 Critical Path Analysis  Critical Path: A: ( > ) B: ( > ) Cin: (0 > 0)

EE141 – Project 23 Critical Path Analysis  Critical Path indicated by  Critical transition: A = ; B= ; Cin = 1:Carry generated in the first bit and then ripples through the Multiplexers holding the precomputed values until it reaches the final sum stage and generates sum8. These Inputs ensure that sum 8 has to wait for Carry_out_7 to reach it for the sum to be valid.  Critical path equation : t critical = t setup + 2t carry + 4t mux + t sum.

EE141 – Project 24 Sizing Characteristics To Carryout

EE141 – Project 25 Sizing Optimization 16X Stage Z: LE=1 B= u/1.92u 960n 2.88u/720n 2.4u/1.2u 0.96n 1.2u0.96n 0.48u 16X Gin7 Gin5 Gin0Gin1 Gin2 Gin3 Gin4 Gin6 Pin7 Pin1Pin2 Pin5 Pin3 Pin4 Pin6 Pin0 A Stage V: LE=1, B=1 Stage W: LE=1, B=4 Stage X : LE=4/3, B=1 Stage Y: LE=2, B=1 Area Concern 0.96u/0.48u Size: Manchester Sizing

EE141 – Project 26 Dynamic Functionality Check

EE141 – Project 27 Static Functionality Check S0 S1 S2 S3 S4 S5 S6 S7 Cout

EE141 – Project 28 Layout Techniques  Size :  m 2 (33.00  m x  m)  Critical Path drawn in arrow  Aspect Ratio =  Routing Metal 1 −Horizontal Line −VDD, GND Metal 2: −Vertical Line Metal 3: −Clock Signals FA0FA1FA2FA3 FA7FA6FA5FA4 INPUT BUFFER OUTPUT BUFFER OUTPUT BUFFER OUTPUT BUFFER OUTPUT BUFFER CLOCK CHAIN

EE141 – Project 29 First Stage (2 bits) Third Stage (2 bits) Last Bit (1 bit) Outputs (Buffers) Second Stage (3 bits) Bypass Mux Cout B A P Cout Cmuxout (“Cout ”) Cout S Layout Techniques

EE141 – Project 210 Layout Techniques FA 2FA 1 Buffer FA 3FA 4 Buffer FA 6FA 5 Buffer FA 7FA 8 Buffer