© Digital Integrated Circuits 2nd Design Methodologies Digital Integrated Circuits A Design Perspective Design Methodologies Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic December 10, 2002

© Digital Integrated Circuits 2nd Design Methodologies The Design Productivity Challenge Source: sematech97 A growing gap between design complexity and design productivity 1981 Logic Transistors per Chip (K) Productivity (Trans./Staff-Month)

© Digital Integrated Circuits 2nd Design Methodologies A Simple Processor MEMORY DATAPATH CONTROL INPUT-OUTPUT INPUT/OUTPUT

© Digital Integrated Circuits 2nd Design Methodologies A System-on-a-Chip: Example Courtesy: Philips

© Digital Integrated Circuits 2nd Design Methodologies Impact of Implementation Choices Energy Efficiency (in MOPS/mW) Flexibility (or application scope) None Fully flexible Somewhat flexible Hardwired custom Configurable/Parameterizable Domain-specific processor (e.g. DSP) Embedded microprocessor

© Digital Integrated Circuits 2nd Design Methodologies Design Methodology Design process traverses iteratively between three abstractions: behavior, structure, and geometry More and more automation for each of these steps

© Digital Integrated Circuits 2nd Design Methodologies Implementation Choices Custom Standard Cells Compiled Cells Macro Cells Cell-based Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Array-based Semicustom Digital Circuit Implementation Approaches

© Digital Integrated Circuits 2nd Design Methodologies The Custom Approach Intel 4004 Courtesy Intel

© Digital Integrated Circuits 2nd Design Methodologies Transition to Automation and Regular Structures Intel 4004 (‘71) Intel 8080 Intel 8085 Intel 8286 Intel 8486 Courtesy Intel

© Digital Integrated Circuits 2nd Design Methodologies Cell-based Design (or standard cells) Routing channel requirements are reduced by presence of more interconnect layers

© Digital Integrated Circuits 2nd Design Methodologies Standard Cell — Example [Brodersen92]

© Digital Integrated Circuits 2nd Design Methodologies Standard Cell – The New Generation Cell-structure hidden under interconnect layers

© Digital Integrated Circuits 2nd Design Methodologies Standard Cell - Example 3-input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time

© Digital Integrated Circuits 2nd Design Methodologies Automatic Cell Generation Courtesy Acadabra Initial transistor geometries Placed transistors Routed cell Compacted cell Finished cell

© Digital Integrated Circuits 2nd Design Methodologies A Historical Perspective: the PLA x 0 x 1 x 2 AND plane x 0 x 1 x 2 Product terms OR plane f 0 f 1

© Digital Integrated Circuits 2nd Design Methodologies Two-Level Logic Inverting format (NOR- NOR) more effective Every logic function can be expressed in sum-of-products format (AND-OR) minterm

© Digital Integrated Circuits 2nd Design Methodologies PLA Layout – Exploiting Regularity V DD GND  And-Plane Or-Plane

© Digital Integrated Circuits 2nd Design Methodologies Breathing Some New Life in PLAs River PLAs  A cascade of multiple-output PLAs.  Adjacent PLAs are connected via river routing. No placement and routing needed. Output buffers and the input buffers of the next stage are shared. Courtesy B. Brayton

© Digital Integrated Circuits 2nd Design Methodologies Experimental Results Layout of C2670 Network of PLAs, 4 layers OTC River PLA, 2 layers no additional routing Standard cell, 2 layers channel routing Standard cell, 3 layers OTC Area: RPLAs (2 layers) 1.23 SCs (3 layers) , NPLAs (4 layers) 1.31 Delay RPLAs 1.04 SCs 1.00 NPLAs 1.09 Synthesis time: for RPLA, synthesis time equals design time; SCs and NPLAs still need P&R. Also: RPLAs are regular and predictable

© Digital Integrated Circuits 2nd Design Methodologies MacroModules 256  32 (or 8192 bit) SRAM Generated by hard-macro module generator

© Digital Integrated Circuits 2nd Design Methodologies “Soft” MacroModules Synopsys DesignCompiler

© Digital Integrated Circuits 2nd Design Methodologies “Intellectual Property” A Protocol Processor for Wireless

© Digital Integrated Circuits 2nd Design Methodologies Semicustom Design Flow HDL Logic Synthesis Floorplanning Placement Routing Tape-out Circuit Extraction Pre-Layout Simulation Post-Layout Simulation Structural Physical Behavioral Design Capture Design Iteration

© Digital Integrated Circuits 2nd Design Methodologies The “Design Closure” Problem Courtesy Synopsys Iterative Removal of Timing Violations (white lines)

© Digital Integrated Circuits 2nd Design Methodologies Integrating Synthesis with Physical Design Physical Synthesis RTL(Timing) Constraints Place-and-Route Optimization Artwork Netlist with Place-and-Route Info Macromodules Fixed netlists

© Digital Integrated Circuits 2nd Design Methodologies Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Array-based Late-Binding Implementation

© Digital Integrated Circuits 2nd Design Methodologies Gate Array — Sea-of-gates Uncommited Cell Committed Cell (4-input NOR)

© Digital Integrated Circuits 2nd Design Methodologies Sea-of-gate Primitive Cells Using oxide-isolationUsing gate-isolation

© Digital Integrated Circuits 2nd Design Methodologies Example: Base Cell of Gate-Isolated GA From Smith97

© Digital Integrated Circuits 2nd Design Methodologies Example: Flip-Flop in Gate-Isolated GA From Smith97

© Digital Integrated Circuits 2nd Design Methodologies Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K (0.6  m CMOS) Courtesy LSI Logic

© Digital Integrated Circuits 2nd Design Methodologies The return of gate arrays? metal-5 metal-6 Via-programmable cross-point programmable via Via programmable gate array (VPGA) [Pileggi02] Exploits regularity of interconnect

© Digital Integrated Circuits 2nd Design Methodologies Prewired Arrays Classification of prewired arrays (or field- programmable devices):  Based on Programming Technique  Fuse-based (program-once)  Non-volatile EPROM based  RAM based  Programmable Logic Style  Array-Based  Look-up Table  Programmable Interconnect Style  Channel-routing  Mesh networks

© Digital Integrated Circuits 2nd Design Methodologies Fuse-Based FPGA antifuse polysiliconONO dielectric n + antifuse diffusion 2 l From Smith97 Open by default, closed by applying current pulse

© Digital Integrated Circuits 2nd Design Methodologies Array-Based Programmable Logic PLAPROMPAL O 1 O 2 O 3 Programmable AND array Programmable OR array O 1 O 2 O 3 Programmable AND array Fixed OR array Indicates programmable connection Indicates fixed connection

© Digital Integrated Circuits 2nd Design Methodologies Programming a PROM f 0 1X 2 X 1 X 0 f 1 NA : programmed node

© Digital Integrated Circuits 2nd Design Methodologies More Complex PAL From Smith97 i inputs, j minterms/macrocell, k macrocells

© Digital Integrated Circuits 2nd Design Methodologies 2-input mux as programmable logic block F A0 B S 1 Configuration ABSF= X1X 0Y1Y 0YXXY X0Y Y0X Y1XX 1 Y 10X 10Y 1111 X Y

© Digital Integrated Circuits 2nd Design Methodologies Logic Cell of Actel Fuse-Based FPGA

© Digital Integrated Circuits 2nd Design Methodologies Look-up Table Based Logic Cell

© Digital Integrated Circuits 2nd Design Methodologies LUT-Based Logic Cell Courtesy Xilinx D 4 C 1....C 4 x xxxxx D 3 D 2 D 1 F 4 F 3 F 2 F 1 Logic function of xxx Logic function of xxx Logic function of xxx xx 4 x xx xxxx H P Bits control Bits control Multiplexer Controlled by Configuration Program x x x x xx x xxxx x xx xxxx xx x x Xilinx 4000 Series Figure must be updated

© Digital Integrated Circuits 2nd Design Methodologies Array-Based Programmable Wiring Input/output pinProgrammed interconnection Interconnect Point Horizontal tracks Vertical tracks Cell

© Digital Integrated Circuits 2nd Design Methodologies Mesh-based Interconnect Network Switch Box Connect Box Interconnect Point Courtesy Dehon and Wawrzyniek

© Digital Integrated Circuits 2nd Design Methodologies Transistor Implementation of Mesh Courtesy Dehon and Wawrzyniek

© Digital Integrated Circuits 2nd Design Methodologies Hierarchical Mesh Network Use overlayed mesh to support longer connections Reduced fanout and reduced resistance Courtesy Dehon and Wawrzyniek

© Digital Integrated Circuits 2nd Design Methodologies EPLD Block Diagram Macrocell Primary inputs Courtesy Altera

© Digital Integrated Circuits 2nd Design Methodologies Altera MAX From Smith97

© Digital Integrated Circuits 2nd Design Methodologies Altera MAX Interconnect Architecture row channelcolumn channel LAB Courtesy Altera Array-based (MAX ) Mesh-based (MAX 9000)

© Digital Integrated Circuits 2nd Design Methodologies Field-Programmable Gate Arrays Fuse-based Standard-cell like floorplan

© Digital Integrated Circuits 2nd Design Methodologies Xilinx 4000 Interconnect Architecture CLB 8484 Quad Single Double Long Direct Connect Direct Connect QuadLongGlobal Clock LongDoubleSingleGlobal Clock Carry Chain Long 1244 Courtesy Xilinx

© Digital Integrated Circuits 2nd Design Methodologies RAM-based FPGA Xilinx XC4000ex Courtesy Xilinx

© Digital Integrated Circuits 2nd Design Methodologies A Low-Energy FPGA (UC Berkeley)  Array Size: 8x8 (2 x 4 LUT)  Power Supply: 1.5V & 0.8V  Configuration: Mapped as RAM  Toggle Frequency: 125MHz  Area: 3mm x 3mm

© Digital Integrated Circuits 2nd Design Methodologies Larger Granularity FPGAs  1-mm 2-metal CMOS tech  1.2 x 1.2 mm 2  600k transistors  208-pin PGA  fclock = 50 MHz  P av = 3.6 5V  Basic Module: Datapath PADDI-2 (UC Berkeley)

© Digital Integrated Circuits 2nd Design Methodologies Design at a crossroad System-on-a-Chip RAM 500 k Gates FPGA + 1 Gbit DRAM Preprocessing Multi- Spectral Imager  C system +2 Gbit DRAM Recog- nition Analog 64 SIMD Processor Array + SRAM Image Conditioning 100 GOPS  Embedded applications where cost, performance, and energy are the real issues!  DSP and control intensive  Mixed-mode  Combines programmable and application-specific modules  Software plays crucial role

© Digital Integrated Circuits 2nd Design Methodologies Addressing the Design Complexity Issue Architecture Reuse Reuse comes in generations Source: Theo Claasen (Philips) – DAC 00

© Digital Integrated Circuits 2nd Design Methodologies Architecture ReUse  Silicon System Platform  Flexible architecture for hardware and software  Specific (programmable) components  Network architecture  Software modules  Rules and guidelines for design of HW and SW  Has been successful in PC’s  Dominance of a few players who specify and control architecture  Application-domain specific (difference in constraints)  Speed (compute power)  Dissipation  Costs  Real / non-real time data

© Digital Integrated Circuits 2nd Design Methodologies Platform-Based Design  A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer  New platforms will be defined at the architecture-micro-architecture boundary  They will be component-based, and will provide a range of choices from structured-custom to fully programmable implementations  Key to such approaches is the representation of communication in the platform model “Only the consumer gets freedom of choice; designers need freedom from choice” (Orfali, et al, 1996, p.522) Source:R.Newton

© Digital Integrated Circuits 2nd Design Methodologies Berkeley Pleiades Processor 0.25um 6-level metal CMOS 5.2mm x 6.7mm 1.2 Million transistors 40 MHz at 1V 2 extra supplies: 0.4V, 1.5V 1.5~2 mW power dissipation Interface Reconfigurable Data-path FPGA ARM8 Core

© Digital Integrated Circuits 2nd Design Methodologies Heterogeneous Programmable Platforms Xilinx Vertex-II Pro Courtesy Xilinx High-speed I/O Embedded PowerPc Embedded memories Hardwired multipliers FPGA Fabric

© Digital Integrated Circuits 2nd Design Methodologies Summary  Digital CMOS Design is kicking and healthy  Some major challenges down the road caused by Deep Sub-micron  Super GHz design  Power consumption!!!!  Reliability – making it work Some new circuit solutions are bound to emerge  Who can afford design in the years to come? Some major design methodology change in the making!

© Digital Integrated Circuits 2nd Design Methodologies Insert F - Design synthesis

© Digital Integrated Circuits 2nd Design Methodologies Circuit synthesis  derivation of the transistors schematics from logic functions - complementary CMOS - pass transistor - dynamic - DCVSL (differential cascode voltage switch logic)  transistor sizing - performance modeling using RC equivalent circuits- layout generation  synthesis not popular due to designers reluctance

© Digital Integrated Circuits 2nd Design Methodologies Logic synthesis  state transition diagrams, FSM, schematics, Boolean equations, truth tables, and HDL used  synthesis - combinational or sequential - multi level, PLA, or FPGA  logic optimization for - area, speed, power - technology mapping

© Digital Integrated Circuits 2nd Design Methodologies Logic optimization  Expresso - two level minimization tool (UCB)  state minimization and state encoding  MIS - multilevel logic synthesis (UCB) Example : S = (A  B) C i C o = AB + AC i + BC i

© Digital Integrated Circuits 2nd Design Methodologies Logic optimization Multilevel implementation of adder generated by MIS II cell library from University of Mississippi

© Digital Integrated Circuits 2nd Design Methodologies Architecture synthesis  behavioral or high level synthesis  optimizing translation e.g. pipelining  Cathedral and HYPER tools  HYPER tutorial and synthesis example:

© Digital Integrated Circuits 2nd Design Methodologies Architecture synthesis example

© Digital Integrated Circuits 2nd Design Methodologies Architecture synthesis

© Digital Integrated Circuits 2nd Design Methodologies Emerging Technologies

Complementary Orthogonal Stacked MOS - COSMOS  Stack two MOSFETs under a common gate  Improve only hole mobility by using strained SiGe channel –pMOS transconductance equal to nMOS  Reduce parasitics due to wiring and isolating the sub-nets Conventional CMOS Complementary Orthogonal Stacked MOS Savas Kaya

Technology Base  Strained Si/SiGe layers  Built-in strain traps more carriers and increases mobility –Equal+high electron and hole mobilities (Jung et al.,p.460,EDL’03)  SOI (silicon-on-Insulator) substrates  active areas on buried oxide (BOX) layer  Reduces unwanted DC leakage and AC parasitics Mizuno et al., p.988, TED’03 Cheng et al., p.L48, SST’04

COSMOS Structure  Single common gate: mid-gap metal or poly-SiGe  Ultra-thin channels: 2-6nm to control threshold/leakage  Strained Si 1-x Ge x for holes (x  0.3)  Strained or relaxed Si for electrons  Substrate: SOI

COSMOS Structure - 3D View I  Single gate stack: mid-gap metal or poly-SiGe  Must be engineered for a symmetric threshold In units of  m

COSMOS Structure - 3D View II  Conventional self-aligned contacts  Doped S/D contacts: p- (blue) or n- (red) type  Inter-dependence between gate dimensions:

© Digital Integrated Circuits 2nd Design Methodologies COSMOS Gate Control  A single gate to control both channels  High-mobility strained Si 1-x Ge x (x  0.3) buried hole channel –High Ge% eliminates parallel conduction and improves mobility –Lowers the threshold voltage V T  Electrons are in a surface channel  Requires fine tuning for symmetric operation

© Digital Integrated Circuits 2nd Design Methodologies 3D Characteristics: 40nm Device  Symmetric operation  No QM corrections –Lower VT  Features in sub-threshold operation –Related to p-i-n parasitic diode included in 3D

COSMOS Inverter Top viewPeel-off top views  No additional processing  Just isolate COSMOS layers and establish proper contacts  Significantly shorter output metallization

3D TCAD Verification  Inverter operation verified in 3D 40nm COSMOS NOT gate driving C L =1fF load

Applications  Low power static CMOS:  Should outperform conventional devices in terms of speed –Multiple input circuit example: NOR gate  Area tight designs :  FPGA, Sensing/testing,  power etc. ?