E-Voting Machine Final Presentation Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober Design Manager Randal Hong Wed, Dec 3 Secure Electronic Voting Terminal

Marketing Project Description Behavior Description Design Process Floorplan Schematics Layout Verification Issues Specification Conclusion Presentation Outline

Early days, ballots were hand-counted Nowadays, voting machines were invented to count votes more efficiently Major voting machines in market currently Optical Scan Direct Recording Electronic (DRE) Methods of Counting Ballots DRE MachineOptical Scan Machine

Optical Scan Scan marked paper ballots and tally the result Cons: Voting system configuration files and removable media Exchange blank ballot Expensive Existing Systems and Falldowns DRE (Direct Recording Electronic) Records votes by means of a ballot display which can be activated by the voter Voting data stored in a removable memory component In 2004, 28.9% of the registered voters in the U.S. used DRE system. Cons: Security of the DRE software Expensive

It’s similar to DRE, but our unit does not store any information Data is transmitted using 32-bit encryption Administrator initializes machine using temporary key Increased speed Mainly it’s much cheaper!!! Our Voting Machine

$1.1 million to buy 200 optical scan voting machines at Centre County, Bellefonte, PA Each DRE machine costs between $2500 and $3500 Voter-verified paper ballot printer could add as much as $1000 Touch screen $300 Fingerprint scanner $40 Printer $40 Id card reader $20 Our chip $10 Packaging $45 Manufacturing $125 Total unit price $600 Comparison

voters at 2008 Presidential Election Allegheny county, PA: 1321 polling places registered voters about 4500 voting machines About 159 people per machine For 2008 election total number of voting machines estimated: $600 * = $ = $361million Source: Pittsburgh tribune-review Market Size

Storing votes in a central machine but not in local voting machines Integrated 32-bit TEA encryption Write-in ability Hard copy of vote Fingerprint scanner Simplicity Functional Overview

8-bit Databus Compact design FSM state encoders Integer based TEA encryption Key Features

Behavioral Algorithm Fingerprint Message ROM Key SRAM Display COMMs ID SRAM User input Choice SRAM cardTx_check

Emphasis on low cost  small area C – Test encryption/decryption and monitored cycling of 8 cipher iterations. Verilog – Hardware implementation of each block in FSMs and Comms. Floorplan - Addition of many flexible logic blocks and buffers later significantly updated floorplan. Schematics – Updated as we ran the simulation and debugged timing and transistor sizing errors. Layout – Updated as we ran extractedRC simulation with reasonable load capacitances. Design Process Overview

Input Data: v = 0x12 34 Key = 0x77 8c ae 38 Iteration: 0x20 eb Sum: 0xa00 Iteration: 0x7f c5 Sum: 0x1400 Iteration: 0xf 6e Sum: 0x1e00 Iteration: 0xc5 73 Sum: 0x2800 Iteration: 0x20 2a Sum: 0x3200 Iteration: 0xd0 6a Sum: 0x3c00 Iteration: 0xc2 9c Sum: 0x4600 Iteration: 0xfd 58 Sum: 0x5000 Encoded data = 0xfd 58 Iteration: 0xc2 9c Sum: 0x4600 Iteration: 0xd0 6a Sum: 0x3c00 Iteration: 0x20 2a Sum: 0x3200 Iteration: 0xc5 73 Sum: 0x2800 Iteration: 0xf 6e Sum: 0x1e00 Iteration: 0x7f c5 Sum: 0x1400 Iteration: 0x20 eb Sum: 0xa00 Iteration: 0x12 34 Sum: 0x0 Decoded data = 0x12 34 Used C to write encryption and decryption Feistel cycles for Comms Block using: 16-bit blocks: Two 8-bit inputs 32-bit key: Four 8-bit keys 32 Feistel rounds = 16 cycles Wrote behavioral and structural Verilog to mirror functionality of C file. Design Process C

Verilog – Behavioral and structural implementation of major blocks in FSMs and Comms. Comms: 3 total design iterations as seen. All logic block changes written in Verilog first and functionally tested before migrating to schematics. Floorplan modified in many stages due to concurrent approach of adding small logics and re-simulating as we passed LVS. Design Process Verilog

Selected all standard cell parts keeping in mind low area and power objective. Used many low power flip-flops to drive FSM and Comms. Sized buffers for functionally correct rise/fall times and propagation delay. Continuously simulated and removed glitches before moving to layout. Design Process Schematics

Used minimum wire width sizes for M3+M4 global and databus interconnects. Specific M3, M4 wiring for Databus and interface Simulate and LVS’ed all large independent functional blocks before global routing. For smaller logic we progressively added them to full layout and passed LVS with simulation. Tried to maximize transistor density to achieve area and power goal. Design Process Layout

Floorplan 1 ●Initial floorplan estimates for Comms size was 4X smaller than FSMs and SRAM took half of chip real estate ●Post-Verilog ●Heavy interconnects over FSMs ●The address lines and databus need to be buffered COMMS FSMs SRAMs

Floorplan 2 ●Second floorplan improved major block size estimates. Comms & FSMs ratio 1:1, SRAM width shrunk ●Post-Schematics ●New aspect ratio 2:1 ●135 by 210 ●Doubled size in COMMS Block ●The address lines and data bus are buffered COMMS FSMs SRAMs

Floorplan 3 ●New aspect ratio 1:1 ●147 by 132 ●Post-layout ●Increased size in COMMS ●Decrease in FSM and SRAM ●FSM connects to message ROM, selection counter, tx_check directly and SRAM via databus ●Decoupled SRAM layout to fit new layout Key SRAM Comms FSMs 64 bit SRAM User_ID SRAMChoice SRAM

Floorplan 3.5 ●Need to add key registers and input buffer to Comms, significantly increasing the length. Flip Comms 90 degrees to accommodate new length.

Floorplan 4 ●157 by 141 ●Aspect ratio lengthened vertically slightly ●Comms flipped 90 degrees ●Addition of integrated key registers in Comms and input buffer. KEY REGISTERS INPUT BUFFER Key SRAM Random Logic

Final Floorplan ●157 by 141 ●Aspect ratio lengthened vertically slightly. ●Databus attached to FSMs, SRAM, and Comms via horizontal M4 layer. ●Addition of random logic such as TX-check, ROM, User Input, Key SRAM, changes the floorplan next to FSMs. SRAM FSM COMMS Random Logic

Flexible layout design process Important / Complex blocks dictate the overall layout dimensions Design can be adapted to significant changes in major blocks Layout Process COMMs FSMs SRAM

Flexible design process Not hindered by a stiff floorplan Important / Complex blocks can dictate their own dimensions Design adapted to significant changes in major blocks Layout Process COMMs FSMs SRAM

Innovative implementation strategy: “Just put it somewhere” Layout Process

Layout - SRAMs z 64byte / 8byte / 4byte SRAMs Density:.70

Layout - COMMs COMMs Size: 116 x 84 um Density:.31

Layout - FSMs FSMs Size: 38 x 52 um Density:.55

Layout – etc.

Layout CHIP Final Design Size: 157 x 141 um Density:.39

Verification You could just trust us….

Verification Time constraints will not allow us to run a full chip simulation So we need to show that our 4 main blocks: Logically simulate Interact with correct setup/hold/propagation timing Transmit signals with correctly buffered strength COMMs FSMs SRAMs misc

Logical Simulations -COMMs Testing Encryption FSMsmisc COMMs SRAMs

Timing FSMsmisc COMMs SRAMs

Signal Strength FSMsmisc COMMs SRAMs

Verification Test cases overlap in key areas Combined results demonstrate validity COMMs FSMs SRAMs misc

Issues Encountered Buffering databus Timing between state machines Cadence update Getting Spectre to work Flip Flop glitching Merging Cadence directories

Specifications Area -141 µm X 157µm -Aspect Ratio of 1 : Transistor Counts Density transistors/µm 2 Inputs/Outputs - 24 inputs - 16 outputs - 16 I/O’s

E-voting Machine Benefits – Low cost and maintenance – Simple and easy use – Market availability Upcoming dates… – AMD Sponsored Presentation – Dec 3 rd, 2008 – Meeting of the Minds – May 9 th, 2009