1 Pertemuan 6 Element of Physical Design Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01

2 Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menyebutkan element-element dalam physiscal design proses VLSI.

3 Basic Concepts Physical design is the actual process of creating circuits on silicon. Polygon in physical design

4 Layout of Basic Structure Masking sequence o. Start with p-type substrate 1. nWell 2. Active 3. Poly 4. pSelect 5. nSelect 6. Active contact 7. Poly contact 8. Metal 1 9. Via 10. Metal Overglass

5 Layout of Basic Structure n-well p-substrate Cross-section Silicon substrate Active FOX Cross-section WaWa S a-a Active Active pattern W nw S nw-nw Mask set n-well

6 Layout of Basic Structure p n+ Active nSelect FOX nSelect Active S a-n WaWa Cross-section Mask set n+ regions: p+ regions: FOX n-well p+ Active nSelect FOX Cross-section nSelect Active S a-n WaWa Mask set S p-nw

7 Layout of Basic Structure n+ n+l p Cross-section poly L nSelect poly Active W d po Mask set nFET: pFET: Mask set pSelect poly Active W d po n-well p+ p+l n-well Cross-section poly L p

8 Layout of Basic Structure n+ p+ n-well p Active contact Cross-section select Active Active contact d ac, v d ac, h S a-ac Generl mask set select Metal 1 Active S m1-ac W m1 Generl mask set n+ p Cross-section Metal 1 Ox

9 Cell Concepts V DD V SS in out V DD V SS out V DD V SS in1 in2 V DD V SS out V DD V SS in1 in2 X NOT X NAND2 X NOR2 Logic gate as basic cells V DD V SS a b f V DD V SS a f b 2 X NOT + X NAND2 Primitive cells New complex cells

10 Cell Concepts D m1-m1 nWell p-substrate P m1-m1 pFET nFET V DD V SS nWell horizontal V DD V SS vertical

11 Cell Concepts X1X1 nWell V DD V SS D1D1 Horizontal FET nWell V DD V SS D2D2 X2X2 Vertical FET Larger Smaller

12 Cell Concepts Logic cells Metal 1 wiring Metal 1 wiring Vertical metal 2 V DD V SS

13 Cell Concepts Logic cells V DD V SS Inverted Logic cells V DD V SS V DD Logic cells Inverted Logic cells Weinberger image array nWell p-substrate VDDVDD V SS V DD Metal 2 pFET nFET Logic row Logic row FET placement in Weinberger array V DD V SS Metal input Metal output To wiring channel Port placement in a cel

14 Physical Design Logic Gate X X Mp Mn V DD Gnd V DD nWell X X Mp Mn X X NOT GATE

15 RESUME Basic Concepts. Layout of Basic Structure. Cell Concepts. Physical Design Logic Gate.