Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010 7.1 EE4800 CMOS Digital IC Design & Analysis Lecture 7 Midterm Review Zhuo Feng.

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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall EE4800 CMOS Digital IC Design & Analysis Lecture 7 Midterm Review Zhuo Feng

Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall ■ Final Exam Time ► October 6th, morning ► 90 minutes (12:30pm to 1:50pm) ■ Five problems ► Covers the latest six lectures ■ One A4-size cheat sheet ■ No lecture slides or textbooks allowed

Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall ■ CMOS Circuits and Layout ► Complementary CMOS circuits ► Minimum feature size, wiring tracks, design rules ► Stick diagram ► Area estimation ► Diffusion region capacitance (parasitics) minimization ■ MOS I-V Characteristics ► MOSFET capacitor ► Operating regions (cutoff, linear and saturation) ► I-V functions, first order Shockley models ■ MOS DC & Transient Responses ► Pass transistors ► DC transfer curve ► Beta ratio and noise margin ► RC delay models, delay estimation, Elmore delay

Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall ■ Logical Effort ► Normalized delay ► Effort delay and parasitic delay ► Path and stage effort delay ► Transistor sizing using logical effort ► Determine the number of stages for best delay ■ Power Estimation and Reduction ► Instantaneous power, energy and average power ► Energy consumption for an inverter ► Power sources : dynamic and static power sources ► Dynamic power estimation and reduction techqnies ► Switching activity factors