Heterogeneous Integration of III-V Active Devices on a Silicon-on-Insulator Photonic Platform G. Roelkens, J. Brouckaert, J. Van Campenhout, D. Van Thourhout, R. Baets Photonics Research Group – Ghent University/IMEC Sint-Pietersnieuwstraat 41, B-9000 Ghent – Belgium e-mail: gunther.roelkens@intec.ugent.be

Outline Introduction Die-to-wafer bonding for hetero-integration Heterogeneously integrated laser diodes Heterogeneously integrated photodetectors Conclusions and outlook

Introduction Why combine silicon with III-V? silicon  fall back on CMOS technology  high index contrast  no emission nor amplification, yet III-V  superb emission, amplification and detection  full active-passive integration is complex and expensive, still III-V on silicon  combine the best of two worlds  price: bonding technology does it work? can it turn into a manufacturing technology?

Introduction There are several ways to integrate III-V on SOI Flip-chip integration of opto-electronic components  most rugged technology  testing of opto-electronic components in advance  slow sequential process (alignment accuracy)  low density of integration Hetero-epitaxial growth of III-V on silicon  collective process, high density of integration  mismatch in lattice constant, CTE, polar/non-polar  contamination and temperature budget Bonding of III-V epitaxial layers  sequential but fast integration process  high density of integration, collective processing  high quality epitaxial III-V layers

Outline Introduction Die-to-wafer bonding for hetero-integration Heterogeneously integrated laser diodes Heterogeneously integrated photodetectors Conclusions and outlook

III-V/Silicon photonics Bonding of III-V epitaxial layers Molecular die-to-wafer bonding Based on van der Waals attraction between wafer surfaces Adhesive die-to-wafer bonding Uses an adhesive layer as a glue to stick both surfaces Wafer-scale processing of III-V devices III-V die bonding (unprocessed) InP substrate removal SOI Waveguide wafer

III-V/Silicon photonics Bonding of III-V epitaxial layers Molecular die-to-wafer bonding Based on van der Waals attraction between wafer surfaces Requires “atomic contact” between both surfaces - very sensitive to particles - very sensitive to roughness - very sensitive to contamination of surfaces Adhesive die-to-wafer bonding Uses an adhesive layer as a glue to stick both surfaces Requirements are more relaxed compared to Molecular - glue compensates for particles (some) - glue compensates for roughness (all) - glue allows (some) contamination of surfaces While established technology for SOI, III-Vs often do not meet the requirements for molecular bonding

DVS-BCB satisfies these requirements Bonding Technology Requirements for the adhesive for bonding Optically transparent High thermal stability (post-bonding thermal budget) Low curing temperature (low thermal stress) No outgassing upon curing (void formation) Resistant to all kinds of chemicals Si CH3 O 1,3-divinyl-1,1,3,3-tetramethyldisiloxane-bisbenzocyclobutene 400C 250C <0.1dB/cm OK HCl,H2SO4,H2O2,… DVS-BCB satisfies these requirements

Solvent evap + prepolymerization DVS-BCB curing (pressurized) Bonding Technology Overview of the bonding process Die/wafer cleaning most critical step in processing SOI wafer: standard clean – 1 (H2SO4:H2O2:H2O @70C) Lifts off particles from surface and prevents redeposition InP/InGaAsP: removal of sacrificial InP/InGaAs layer pair DVS-BCB DVS-BCB Si-substrate SiO2 Si DVS-BCB DVS-BCB Wafer cleaning DVS-BCB coating Solvent evap + prepolymerization Die attachment DVS-BCB curing (pressurized)

Bonding Technology Overview of the bonding process Optical SOI wafer Thinning: - mechanical grinding - wet etching till etch stop layer reached (HCl) After bonding After thinning Cross-section

InP/InGaAsP epitaxial layer stack InP-InGaAsP epitaxial layer stack Bonding Technology Cross-sectional image of III-V/Silicon substrate InP/InGaAsP epitaxial layer stack InP-InGaAsP epitaxial layer stack DVS-BCB DVS-BCB Si Si WG SiO2 200nm Si SiO2 200nm

Towards integrated devices Laser diodes and photodetectors have to be fabricated in bonded III-V layer and coupled to SOI circuit below What architecture is used for the laser diode / photodetector? How is light efficiently coupled between III-V and SOI layer? Performance degradation of bonded active devices? Silicon substrate Oxide buffer layer Silicon waveguide layer InP/InGaAsP layer stack

Outline Introduction Die-to-wafer bonding for hetero-integration Heterogeneously integrated laser diodes Fabry-Perot lasers Microring lasers Heterogeneously integrated photodetectors Conclusions and outlook

Integrated Devices: laser diode Integrated laser diodes Fabry-Perot laser cavity by etching InP/InGaAsP laser facets Inverted adiabatic taper coupling approach Laser beam

Integrated Devices: laser diode Integrated laser diodes Fabry-Perot laser cavity by etching InP/InGaAsP laser facets Inverted adiabatic taper coupling approach

Integrated Devices: laser diode Integrated laser diodes Only pulsed operation due to high thermal resistivity DVS-BCB Integration of a heat sink to improve heat dissipation Continuous wave operation achieved this way

Integrated Devices: laser diode Integrated laser diodes Microlasers SiO2/BCB ts = 0nm ts = 50nm ts = 100nm microdisk diameter D [mm] bend loss [/cm] Simulation results “Fundamental Whispering Gallery Modes” TE-pol Meep FDTD

CW Microdisk Laser integrated with SOI wire 7.5-mm devices exhibit continuous-wave lasing Threshold current Ith = 0.6mA, voltage Vth = 1.5-1.7V, up to 7mW CW, 100 mW pulsed (coupled into SOI wire) J. Van Campenhout et al (Ghent University-IMEC, INL, CEA-LETI), OFC 2007 and Optics Express, p.6744-6749 (2007)

Integrated Devices: laser diode Integrated laser diodes Microlasers (7.5um devices) Threshold current Ith = 0.6mA, voltage Vth = 1.5-1.7V slope efficiency = 15mW/mA, up to 7mW (Pulsed regime: up to 100mW peak power) Thermal roll-over can be shifted to higher drive current levels through the incorporation of an integrated heat sink as for the Fabry-Perot laser diodes

On-Chip Optical Interconnect “Adding a compact and efficient optical link to a silicon chip, by heterogeneous integration” SOI waveguide SOI Optical Interconnect layer Electrical Interconnect layer Silicon transistor layer microdetector microlaser III-V material → European research programme PICMOS (Photonic Interconnect Layer on CMOS by Waferscale Integration, FP6-2002-IST-1-002131)

Outline Introduction DVS-BCB die-to-wafer bonding for hetero-integration Heterogeneously integrated laser diodes Heterogeneously integrated photodetectors p-i-n MSM Conclusions and outlook

Integrated Devices: detectors Integrated photodetectors Side-coupled p-i-n photodetector Identical structure as bonded Fabry-Perot laser diode Relatively good responsivity (0.23A/W) Large number of processing steps – compatible with laser

Integrated Devices: detectors Integrated photodetectors Vertical incidence p-i-n photodetector Coupling using a diffraction grating Low experimental responsivity (0.02A/W) but due to design Smaller number of processing steps – more compact design DVS- BCB layer Oxide buffer layer

Integrated Devices: detectors Integrated photodetectors Evanescently coupled MSM detector Small number of processing steps High experimental responsivity (1.0A/W) Compact devices Epitaxial layer structure not compatible with laser epitaxy

Integrated Devices: detectors Integrated photodetectors Evanescently coupled MSM detector Directional coupling between detector waveguide and SOI waveguide (3μm) SOI waveguide contact window Ti/Au contact 40μm 2 coplanar Schottky contacts InAlGaAs Graded schottky contact layer InGaAs absorption layer

Integrated Devices: detectors Integrated photodetectors Evanescently coupled MSM detector 25μm long detector Wide spectral range (limited by bandgap wavelength of InGaAs @ 1.65μm) 25μm long detector R = 1A/W (1550nm), IQE = 80% (5V bias) Idark = 3nA (5V bias)

Outline Introduction DVS-BCB die-to-wafer bonding for hetero-integration Heterogeneously integrated laser diodes Heterogeneously integrated photodetectors Conclusions and outlook

Conclusions and outlook Heterogeneous III-V/Silicon PICs hold the promise to combine best of both worlds, resulting in complex active/passive integrated optical circuits. Bonding technology is an enabling technology to achieve this. Adhesive die-to-wafer bonding is a robust technology compatible with modest surface quality of III-V surfaces Proof-of-principle components have been demonstrated, illustrating the benefits of this technology. The design and characterization of more complex integrated circuits is on the way.

Acknowledgements PICMOS consortium, in particular CEA-LETI, TRACIT and INL Lyon for co-developing the InP/Si microlaser IMEC CMOS pilot line for fabricating the SOI photonic circuits ePIXnet Silicon Photonics Platform (IMEC+LETI) for organizing MPW runs on a a cost-sharing basis (www.siliconphotonics.eu)