°Instructor: Prof. Ginnie Lo  GTF: Amir Rasti °Prerequisite: CIS212, MATH231 Note: These slides are heavily based on the slides used in previous years. However, we have made changes, deletion, and additions to them. CIS 314 : Computer Organization Lecture 1 – Introduction

What is this course all about? Fundamental concepts about how a computer works – The five basic components of a computer – How everything boils down to 1’s and 0’s – How a computer program is executed by the hardware – Machine language: the basic language that a computer ‘understands’ – How the basic instructions in a machine language are carried out by the computer hardware 2CIS314 - Fall 2010

What is this course all about? (cont.) Fundamental concepts about how a computer works – A little about how a program in a high level language like C gets translated into machine language (More “what” than “how”. The how is really the topic of our compilers course) – How to measure computer performance – How the computer architecture is designed to maximize performance: CPU design: Pipelining Memory design: Caching 3CIS314 - Fall 2010

What technical skills in 314? Assembly Language Programming in MIPS – A side effect of understanding the key ideas (not the goal of this course) Logic Design – A little about how to design computer components from logic gates Unix Basics – Basic commands and tools 4CIS314 - Fall 2010

Textbook Required: Computer Organization and Design: The Hardware/Software Interface, Fourth Edition, Patterson and Hennessy (P&H). The third edition is far inferior, and is not suggested. The book should be available in the bookstore We’ll use both the textbook and the CD included with it Keep reading the relevant chapter as we cover each topic 5CIS314 - Fall 2010

Weekly Schedule Lectures - Principles and concepts – MWF 10-10: Deady – Prof. Lo Office Hrs: Mon, Thurs 2-3:30 and by appt – Amir Rasti Office Hrs: Tue 2-3:30, Thu 11-12:30 Discussion Sessions – Assignments – F 11:00 – 11: Klamath – F 13:00 – 13: Klamath Please come to class on time Class schedule is available online Check “announcement” part of the class web page Grades on Blackboard (blackboard.uoregon.edu) 6CIS314 - Fall 2010

Course Assignments Homework assignments; due in lectures, returned in discussions NO LATE ASSIGNMENT IS ACCEPTED! But you can drop lowest HW score. Programming assignments – You will use the SPIM simulator. Grading is based on how your program runs on the department machines. – Get CS UNIX accounts ASAP ( In-class Quizzes (you can drop lowest quiz score) 7CIS314 - Fall 2009

Two Course Exams – Midterm: Monday Nov 3rd in class One sheet of notes allowed Review session TBD – Final: Wednesday Dec 10:15 AM One sheet of notes allowed Review session TBD 8CIS314 - Fall 2010

GRADING 15% Homework Assignments 10% Quizzes 15% Programming assignments 30% Midterm 30% Final 9CIS314 - Fall 2010

Course Problems…Cheating What is cheating? – Studying together in groups is encouraged. – Turned-in work must be completely your own. – Common examples of cheating: saving somebody else’s work to drive/remote site, take homework from box and copy, person asks to borrow solution “just to take a look”, copying an exam question, … – Both “giver” and “receiver” are equally culpable Cheating on homework/projects: negative points for that assignment (e.g., if it’s worth 10 pts, you get -10) Cheating on exams: F in the course. Every offense will be referred to the Office of Student Judicial Affairs ( 10CIS314 - Fall 2010

What is Computer Organization? Where is the HW/SW Interface? *Coordination of many levels (layers) of abstraction I/O systemProcessor Compiler Operating System (Unix) Application (C program) Digital Design Circuit Design Instruction Set Architecture Datapath & Control Transistors Memory Hardware Software Assembler 11CIS314 - Fall 2010

Levels of Representation High Level Language Program (e.g., C) Assembly Language Program (e.g.,MIPS) Machine Language Program (MIPS) Hardware Architecture Description (e.g., Verilog Language) Compiler Assembler Machine Interpretation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw $t0, 0($2) lw $t1, 4($2) sw $t1, 0($2) sw $t0, 4($2) Logic Circuit Description (Verilog Language) Architecture Implementation wire [31:0] dataBus; regFile registers (databus); ALU ALUBlock (inA, inB, databus); wire w0; XOR (w0, a, b); AND (s, w0, a); 12CIS314 - Fall 2010

Anatomy: 5 components of any Computer Personal Computer Processor Computer Control (“brain”) Datapath (“brawn”) Memory (where programs, data live when running) Devices Input Output Keyboard, Mouse Display, Printer Disk (where programs, data live when not running) 13CIS314 - Fall 2010

Overview of Physical Implementations Integrated Circuits (ICs) – Combinational logic circuits, memory elements, analog interfaces. Printed Circuits (PC) boards – substrate for ICs and interconnection, distribution of CLK, Vdd, and GND signals, heat dissipation. Power Supplies – Converts line AC voltage to regulated DC low voltage levels. Chassis (rack, card case,...) – holds boards, power supply, provides physical interface to user or other systems. Connectors and Cables. The hardware out of which we make systems. 14CIS314 - Fall 2010

Integrated Circuits (2003 state-of-the-art) Primarily Crystalline Silicon 1mm - 25mm on a side feature size ~ 0.13µm = 0.13 x m M transistors ( M “logic gates”) conductive layers “CMOS” (complementary metal oxide semiconductor) - most common. °Package provides: spreading of chip-level signal paths to board-level heat dissipation. °Ceramic or plastic with gold wires. Chip in Package Bare Die 15CIS314 - Fall 2010

Printed Circuit Boards fiberglass or ceramic 1-20 conductive layers 1-20in on a side IC packages are soldered down. 16CIS314 - Fall 2010

Technology Trends: Memory Capacity (Single-Chip DRAM) year size (Mbit) Now 1.4X/yr, or 2X every 2 years. 8000X since 1980! 17CIS314 - Fall 2010

Technology Trends: Microprocessor Complexity 2X transistors/Chip Every 1.5 years Called “Moore’s Law” Alpha 21264: 15 million Pentium Pro: 5.5 million PowerPC 620: 6.9 million Alpha 21164: 9.3 million Sparc Ultra: 5.2 million Moore’s Law Athlon (K7): 22 Million 18CIS314 - Fall 2010

Moore’s Law Gordon Moore - co-founder of Intel observed and predicted a trend: Density of data on a chip would double every year (Specifically density of transistors on an integrated circuit) True for 4 decades. Has slowed a little to double every 18 months. Expected to continue for at least two more decades. Implications: increased performance, decreased cost 19CIS314 - Fall 2010

Technology Trends: Processor Performance 1.54X/yr Intel P MHz (Fall 2001) We’ll talk about processor performance later on… year Performance measure

Computer Technology - Dramatic Change! Memory – DRAM capacity: 2x / 2 years (since ‘96); 64x size improvement in last decade. Processor – Speed 2x / 1.5 years (since ‘85); 100X performance in last decade. Disk – Capacity: 2x / 1 year (since ‘97) 250X size in last decade. 21CIS314 - Fall 2010

Computer Technology - Dramatic Change! State-of-the-art PC when you graduate: (at least…) – Processor clock speed: 3-4 GHz – Number of cores: 2-4 – Memory capacity: 4.0 GB – Disk capacity: 2000 GB (2.0 TB = TeraBytes) – New units needed for the future! (Kilo, Mega, Giga, Tera, Peta, Exa, Zetta, Yotta = ) 22CIS314 - Fall 2010

Summary of HW Changes Continued rapid improvement in computing – 2Xevery 2.0 years in memory size; every 1.5 years in processor speed; every 1.0 year in disk capacity; – Moore’s Law enables processor (2X transistors/chip ~1.5 yrs) 5 classic components of all computers Control Datapath Memory Input Output Processor }} I/O 23CIS314 - Fall 2010

Instruction Set Architectures Different CPUs implement different sets of instructions. The set of instructions a particular CPU implements is an Instruction Set Architecture (ISA). – Examples: Intel 80x86 (Pentium 4), IBM/Motorola PowerPC (Macintosh), MIPS, Intel IA64,...

Instruction Set Architectures - History Accumulator ISA – One register in the CPU for arithmetic called the accumulator LOAD ACC, X ADD ACC, Y STORE ACC, Z Stack ISA – A stack is used for arithmetic PUSH X PUSH Y ADD POP Z

Instruction Set Architectures General Purpose Register ISA Three types based on where operands for arithmetic operations can come from. – Memory-memory – Register-memory – Register-register (Load/Store) MIPS has a Load/Store ISA

Instruction Set Architectures Early trend was to add more and more instructions to new CPUs to do elaborate operations – VAX architecture had an instruction to multiply polynomials! RISC philosophy: Reduced Instruction Set Computing – Keep the instruction set small and simple, makes it easier to build fast hardware. – Let software do complicated operations by composing simpler ones.

RISC Architectures Fixed instruction lengths Load/store instruction sets Limited addressing modes (ways to access variables in memory) Limited operations Sun SPARC, IBM PowerPC, MIPS

A Few Famous Computer Hardware Designers: CIS314 - Fall John Hennessy, President Stanford University RISC Architecture David Patterson, Prof. UC Berkeley RISC Architecture Stored program architecture RISC and pipelining

MIPS Architecture MIPS – semiconductor company that built one of the first commercial RISC architectures We will study the MIPS architecture in some detail in this class (also used in CIS 429 Computer Architecture) Why MIPS instead of Intel 80x86? – MIPS is simple, elegant. Don’t want to get bogged down in gritty details. – MIPS widely used in embedded apps, x86 little used in embedded; mostly PCs.

A few of my favorite computers CIS314 - Fall

Powerpoint Lecture Slides Credit to – Visiting professor Juan Flores, and former GTF Dayi Zhou – Dan Garcia, UC Berkeley Computer Science department, for many of the slides for this course – Ginnie Lo and Reza Rejaie, UO Computer Science department Slides will be available on-line in.ppt and.pdf formats 32CIS314 - Fall 2010

Mystery Photo Can you identify 3 people in this photo?? CIS314 - Fall