© 2004 Xilinx, Inc. All Rights Reserved Implemented by : Alon Ben Shalom Yoni Landau Project supervised by: Mony Orbach High speed digital systems laboratory Technion - Israel institute of technology department of Electrical Engineering A single semester Project A single semester Project Final Presentation Spring 2007

© 2004 Xilinx, Inc. All Rights Reserved Agenda Project Goals Devices & Environment Block Diagram Config Module Capture Module Frame capture algorithm Troubleshooting & Solutions Conclusions

© 2004 Xilinx, Inc. All Rights Reserved Project Goals Capture a single frame through a CCD camera and forward it to SOPC memory (BRAM) using Virtex II PRO. Study VirtexIIpro development environment ( EDK 9.1) and the design tools ( HDL designer, Modelsim ) External power supply ov5017 Adapter XUP Vertex II PRO CCD Camera

© 2004 Xilinx, Inc. All Rights Reserved CCD Camera - ¼ ” Monochrome digital camera The M4088 digital camera is based on OV5017 CCD chip manufactured by OmniVision. Chip Interface : M4088 camera module. M4088 Development Environment FPGA - Xilinx VirtexIIpro EDK - platform studio 9.1 VHDL code was created using HDL Designer Logic simulation - Modelsim Devices & Enviroment

© 2004 Xilinx, Inc. All Rights Reserved Adapter is composed of 2 “Fairchild” buffers Devices & Enviroment(Cont.)

© 2004 Xilinx, Inc. All Rights Reserved Block Diagram SOPC structure Module is connected directly to PLB (Max throughput) CPU, using burst, samples core data and writes it to memory OCM – CPU’s instruction memory

© 2004 Xilinx, Inc. All Rights Reserved Core Block Diagram We need to mux the signals since the high-Z state is not available inside the VERTEX IP. Muxed signals are connected to the same connectors Config Capture FPGA inputs MUXMUX Camera outputs Address,OEB,CSB,WEB Camera outputs Data FPGA output Data,ready Camera inputs

© 2004 Xilinx, Inc. All Rights Reserved Config Module In order to get a frame there’s a need to configure the camera to user needs. It’s done by writing to a specific register in camera at address “0101”. The following figure illustrates a single byte write to a specific register.

© 2004 Xilinx, Inc. All Rights Reserved Config Module (Cont.) The user configure the camera through C code. Data is delivered to the Config Module by the CPU, when start signal rise to ‘1’ the module sets The relevant data to camera and the configuration is implemented. The module is a state machine setting the data to camera

© 2004 Xilinx, Inc. All Rights Reserved From C command to Module 32 bit registers were allocated by EDK Data is transferred from C code through the registers to Modules No need to recompile HW whenever data changes C code to Module interaction example

© 2004 Xilinx, Inc. All Rights Reserved After the user configured the camera he sets start to ‘1’ (through C Code), the module starts setting the outputs to camera so the frame data is Received from camera. Frame is composed of 384*288 pixels (pixel is a byte) The following figure illustrates a frame data stream – It’s actually reading A data register Capture Module

© 2004 Xilinx, Inc. All Rights Reserved The Module is composed of several sub modules interacting with each other in Order to synchronize FPGA with camera. Capture Module (Cont.) controller Shift register FIFO coordinator inputs outputs

© 2004 Xilinx, Inc. All Rights Reserved Start rise to ‘1’ – Controller sets the Camera to data stream. When a new frame starts controller send “in_win” signal to shift Register for start storing data and send it to FIFO Shift register counts 4 pixels (pixel=byte), it converts The 4 bytes to a 32 bits word and send a “ready” signal to FIFO FIFO accumulates 8 words (32 bits each), when finished It sends “all_ready” signal to coordinator, which in response raises the “all_reg_trig” signal to FIFO in order to move the 8 words to the second level in the FIFO and signal to the CPU to start reading. Coordinator waits for the CPU to write the Data to memory, when CPU finishes it sends to the Coordinator ACK signal Capture Module – Behavioral Description controller Shift register FIFO coordinator inputs outputs

© 2004 Xilinx, Inc. All Rights Reserved The following diagram illustrates the stages of a frame capture Frame capture algorithm

© 2004 Xilinx, Inc. All Rights Reserved Troubleshooting & Solutions Module was originally connected to OPB - CPU didn’t succeed writing data to memory on time due to the fact it should go over the PLB/OPB bridge (Real time system complication) Module was moved to PLB

© 2004 Xilinx, Inc. All Rights Reserved Troubleshooting & Solutions - Cont’d CPU instruction memory was connected to PLB – Bus is very active Instruction memory was replaced by OCM – Low competition over the PLB resource

© 2004 Xilinx, Inc. All Rights Reserved Troubleshooting & Solutions - Cont’d Read/Write bus access was too slow for data rate Using Read/Write burst bus access to improve throughput Unreliable synchronization signal behavior of camera Logic solution (debouncer) Voltage mismatch between camera to FGPA connectors We built an adapter to resolve this issue

© 2004 Xilinx, Inc. All Rights Reserved Conclusions A better solution for capturing a frame could be moving the data using DMA. This way there were much less bus transactions, therefore a much faster solution.

© 2004 Xilinx, Inc. All Rights Reserved Thank you for your time !