8/22/06 and 8/24/06 ELEC / Lecture 2 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5270/6270) Power Consumption in a CMOS Circuit Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

8/22/06 and 8/24/06ELEC / Lecture 22 Components of Power Dynamic Dynamic Signal transitions Signal transitions Logic activity Logic activity Glitches Glitches Short-circuit Short-circuit Static Static Leakage Leakage P total =P dyn + P stat P tran + P sc + P stat

8/22/06 and 8/24/06ELEC / Lecture 23 Power of a Transition: P tran V DD Ground CLCL R on R=large v i (t) v o (t) i c (t)

8/22/06 and 8/24/06ELEC / Lecture 24 Charging of a Capacitor V C R i(t) i(t) v(t) Charge on capacitor, q(t)=C v(t) Current, i(t)=dq(t)/dt=C dv(t)/dt t = 0

8/22/06 and 8/24/06ELEC / Lecture 25 i(t)=C dv(t)/dt=[V – v(t)] /R dv(t)V – v(t) ───=───── dt RC dv(t) dt ∫ ─────= ∫ ──── V – v(t) RC -t ln [V – v(t)]=──+ A RC Initial condition, t = 0, v(t) = 0 → A = ln V -t v(t)=V [1 – exp(───)] RC

8/22/06 and 8/24/06ELEC / Lecture 26 -t v(t)=V [1 – exp( ── )] RC dv(t) V -t i(t)=C ───=── exp( ── ) dt R RC

8/22/06 and 8/24/06ELEC / Lecture 27 Total Energy Per Charging Transition from Power Supply ∞∞ V 2 -t E trans =∫ V i(t) dt=∫ ── exp( ── ) dt 00 R RC =CV 2

8/22/06 and 8/24/06ELEC / Lecture 28 Energy Dissipated per Transition in Resistance ∞ V 2 ∞ -2t R ∫ i 2 (t) dt=R ── ∫ exp( ── ) dt 0 R 2 0 RC 1 = ─ CV 2 2

8/22/06 and 8/24/06ELEC / Lecture 29 Energy Stored in Charged Capacitor ∞ ∞ -t V -t ∫ v(t) i(t) dt= ∫ V [1-exp( ── )] ─ exp( ── ) dt 0 0 RC R RC 1 = ─ CV 2 2

8/22/06 and 8/24/06ELEC / Lecture 210 Transition Power Gate output rising transition Gate output rising transition Energy dissipated in pMOS transistor = CV 2 /2 Energy dissipated in pMOS transistor = CV 2 /2 Energy stored in capacitor = CV 2 /2 Energy stored in capacitor = CV 2 /2 Gate output falling transition Gate output falling transition Energy dissipated in nMOS transistor = CV 2 /2 Energy dissipated in nMOS transistor = CV 2 /2 Energy dissipated per transition = CV 2 /2 Energy dissipated per transition = CV 2 /2 Power dissipation: Power dissipation: P trans =E trans α f ck =α f ck CV 2 /2 α=activity factor

8/22/06 and 8/24/06ELEC / Lecture 211 Components of Power Dynamic Dynamic Signal transitions Signal transitions Logic activity Logic activity Glitches Glitches Short-circuit Short-circuit Static Static Leakage Leakage P total =P dyn + P stat P tran + P sc + P stat

8/22/06 and 8/24/06ELEC / Lecture 212 Short Circuit Current, i sc (t) Time (ns) 0 1 Amp Volt V DD i sc (t) 0 V i (t) V o (t) V DD - V Tp V Tn tBtB tEtE I scmaxf

8/22/06 and 8/24/06ELEC / Lecture 213 Peak Short Circuit Current Increases with the size (or gain, β) of transistors Increases with the size (or gain, β) of transistors Decreases with load capacitance, C L Decreases with load capacitance, C L Largest when C L = 0 Largest when C L = 0 Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS ’96, Aug. 1996, pp Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS ’96, Aug. 1996, pp

8/22/06 and 8/24/06ELEC / Lecture 214 Short-Circuit Energy per Transition E scf = ∫ t B t E V DD i sc (t)dt = (t E – t B ) I scmaxf V DD /2 E scf = ∫ t B t E V DD i sc (t)dt = (t E – t B ) I scmaxf V DD /2 E scf = t f (V DD - |V Tp | - V Tn ) I scmaxf /2 E scf = t f (V DD - |V Tp | - V Tn ) I scmaxf /2 E scr = t r (V DD - |V Tp | - V Tn ) I scmaxr /2 E scr = t r (V DD - |V Tp | - V Tn ) I scmaxr /2 E scf = 0, when V DD = |V Tp | + V Tn E scf = 0, when V DD = |V Tp | + V Tn

8/22/06 and 8/24/06ELEC / Lecture 215 Short-Circuit Energy Increases with rise and fall times of input Increases with rise and fall times of input Decreases for larger output load capacitance Decreases for larger output load capacitance Decreases and eventually becomes zero when V DD is scaled down but the threshold voltages are not scaled down Decreases and eventually becomes zero when V DD is scaled down but the threshold voltages are not scaled down

8/22/06 and 8/24/06ELEC / Lecture 216 Short-Circuit Power Calculation Assume equal rise and fall times Assume equal rise and fall times Model input-output capacitive coupling (Miller capacitance) Model input-output capacitive coupling (Miller capacitance) Use a spice model for transistors Use a spice model for transistors T. Sakurai and A. Newton, “Alpha-power Law MOSFET model and Its Application to a CMOS Inverter,” IEEE J. Solid State Circuits, vol. 25, April 1990, pp T. Sakurai and A. Newton, “Alpha-power Law MOSFET model and Its Application to a CMOS Inverter,” IEEE J. Solid State Circuits, vol. 25, April 1990, pp

8/22/06 and 8/24/06ELEC / Lecture 217 Short Circuit Power P sc =α f ck E sc

8/22/06 and 8/24/06ELEC / Lecture 218 P sc vs. C C (fF) Decreasing Input rise time 3ns 0% 45% 0.5ns P sc /P total 0.7μ CMOS 3575

8/22/06 and 8/24/06ELEC / Lecture 219 P sc, Rise Time and Capacitance V DD Ground CLCL R on R=large v i (t) v o (t) i c (t)+i sc (t) tftf trtr v o (t) ─── R↑

8/22/06 and 8/24/06ELEC / Lecture 220 i sc, Rise Time and Capacitance -t V DD [ 1- exp ( ───── )] v o (t) R↓ tf (t)C I sc (t) =──── =────────────── R↑ tf (t)

8/22/06 and 8/24/06ELEC / Lecture 221 i scmax, Rise Time and Capacitance Small C Large C tftf 1 ──── R↑ tf (t) i scmax v o (t) i t

8/22/06 and 8/24/06ELEC / Lecture 222 P sc, Rise Times, Capacitance For given input rise and fall times short circuit power decreases as output capacitance increases. For given input rise and fall times short circuit power decreases as output capacitance increases. Short circuit power increases with increase of input rise and fall times. Short circuit power increases with increase of input rise and fall times. Short circuit power is reduced if output rise and fall times are smaller than the input rise and fall times. Short circuit power is reduced if output rise and fall times are smaller than the input rise and fall times.

8/22/06 and 8/24/06ELEC / Lecture 223 Technology Scaling Scaling down 0.7 micron by factors 2 and 4 leads to 0.35 and 0.17 micron technologies Scaling down 0.7 micron by factors 2 and 4 leads to 0.35 and 0.17 micron technologies Constant electric field assumed Constant electric field assumed

8/22/06 and 8/24/06ELEC / Lecture 224 Constant Electric Field Scaling B. Davari, R. H. Dennard and G. G. Shahidi, “CMOS Scaling for High Performance and Low Power—The Next Ten Years,” Proc. IEEE, April 1995, pp B. Davari, R. H. Dennard and G. G. Shahidi, “CMOS Scaling for High Performance and Low Power—The Next Ten Years,” Proc. IEEE, April 1995, pp Other forms of scaling are referred to as constant-voltage and quasi-constant- voltage. Other forms of scaling are referred to as constant-voltage and quasi-constant- voltage.

8/22/06 and 8/24/06ELEC / Lecture 225 Bulk nMOSFET n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon

8/22/06 and 8/24/06ELEC / Lecture 226 Technology Scaling A scaling factor (S ) reduces device dimensions as 1/S. A scaling factor (S ) reduces device dimensions as 1/S. Successive generations of technology have used a scaling S = √2, doubling the number of transistors per unit area. This produced 0.25μ, 0.18μ, 0.13μ, 90nm and 65nm technologies, continuing on to 45nm and 30nm. Successive generations of technology have used a scaling S = √2, doubling the number of transistors per unit area. This produced 0.25μ, 0.18μ, 0.13μ, 90nm and 65nm technologies, continuing on to 45nm and 30nm. A 5% gate shrink (S = 1.05) is commonly applied to boost speed as the process matures. A 5% gate shrink (S = 1.05) is commonly applied to boost speed as the process matures. N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Boston: Pearson Addison-Wesley, 2005, Section

8/22/06 and 8/24/06ELEC / Lecture 227 Constant Electric Field Scaling Device Parameter Scaling Length, L 1/S Width, W 1/S Gate oxide thickness, t ox 1/S Supply voltage, V DD 1/S Threshold voltages, V tn, V tp 1/S Substrate doping, N A S

8/22/06 and 8/24/06ELEC / Lecture 228 Constant Electric Field Scaling (Cont.) Device Characteristic Scaling β W / (L t ox ) S Current, I ds β (V DD – V t ) 2 β (V DD – V t ) 2 1/S Resistance, R V DD / I ds 1 Gate capacitance, C W L / t ox 1/S Gate delay, τ RC 1/S Clock frequency, f 1/ τ S Dynamic power per gate, P CV 2 f 1/S 2 Chip area, A 1/S 2 Power density P/A1 Current density I ds /A S

8/22/06 and 8/24/06ELEC / Lecture 229 Technology Scaling Results Input t r or t f (ns) 1% 70% P sc /P total L=0.7μ, C=40fF % L=0.35μ, C=20fF L=0.17μ, C=10fF 60% 4% 16% 37%

8/22/06 and 8/24/06ELEC / Lecture 230 Effects of Scaling Down 1-16% short-circuit power at 0.7 micron 1-16% short-circuit power at 0.7 micron 4-37% at 0.35 micron 4-37% at 0.35 micron 12-60% at 0.17 micron 12-60% at 0.17 micron Gate delay and rise/fall times decrease with scaling and that prevents short-circuit power from increasing. Gate delay and rise/fall times decrease with scaling and that prevents short-circuit power from increasing. Reference: S. R. Vemuru and N. Steinberg, “Short Circuit Power Dissipation Estimation for CMOS Logic Gates,” IEEE Trans. on Circuits and Systems I, vol. 41, Nov. 1994, pp Reference: S. R. Vemuru and N. Steinberg, “Short Circuit Power Dissipation Estimation for CMOS Logic Gates,” IEEE Trans. on Circuits and Systems I, vol. 41, Nov. 1994, pp

8/22/06 and 8/24/06ELEC / Lecture 231 Summary: Short-Circuit Power Short-circuit power is consumed by each transition (increases with input transition time). Short-circuit power is consumed by each transition (increases with input transition time). Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power). Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power). Increasing the output load capacitance reduces short-circuit power. Increasing the output load capacitance reduces short-circuit power. Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power; completely eliminated when V DD ≤ |V tp |+V tn. Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power; completely eliminated when V DD ≤ |V tp |+V tn.

8/22/06 and 8/24/06ELEC / Lecture 232 Components of Power Dynamic Dynamic Signal transitions Signal transitions Logic activity Logic activity Glitches Glitches Short-circuit Short-circuit Static Static Leakage Leakage

8/22/06 and 8/24/06ELEC / Lecture 233 Leakage Power IGIG IDID I sub I PT I GIDL n+ Ground V DD R DrainSource Gate Bulk Si (p) nMOS Transistor

8/22/06 and 8/24/06ELEC / Lecture 234 Leakage Current Components Subthreshold conduction, I sub Subthreshold conduction, I sub Reverse bias pn junction conduction, I D Reverse bias pn junction conduction, I D Gate induced drain leakage, I GIDL due to tunneling at the gate-drain overlap Gate induced drain leakage, I GIDL due to tunneling at the gate-drain overlap Drain source punchthrough, I PT due to short channel and high drain-source voltage Drain source punchthrough, I PT due to short channel and high drain-source voltage Gate tunneling, I G through thin oxide; may become significant with scaling Gate tunneling, I G through thin oxide; may become significant with scaling

8/22/06 and 8/24/06ELEC / Lecture 235 Subthreshold Current I sub = μ 0 C ox (W/L) V t 2 exp{(V GS –V TH ) / nV t } μ 0 : carrier surface mobility C ox : gate oxide capacitance per unit area L: channel length W: gate width V t = kT/q: thermal voltage n: a technology parameter

8/22/06 and 8/24/06ELEC / Lecture 236 I DS for Short Channel Device I sub = μ 0 C ox (W/L)V t 2 exp{(V GS –V TH + ηV DS )/nV t } V DS = drain to source voltage η: a proportionality factor W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submicron Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp

8/22/06 and 8/24/06ELEC / Lecture 237 Increased Subthreshold Leakage 0V TH ’V TH Log (Drain current) Gate voltage Scaled device IcIc I sub

8/22/06 and 8/24/06ELEC / Lecture 238 Summary: Leakage Power Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power. Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power. For a gate it is a small fraction of the total power; it can be significant for very large circuits. For a gate it is a small fraction of the total power; it can be significant for very large circuits. Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking. Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking. Multiple-threshold devices are used to reduce leakage power. Multiple-threshold devices are used to reduce leakage power.

8/22/06 and 8/24/06ELEC / Lecture 239 A Design Example A battery-operated 65nm digital CMOS device is found to consume equal amounts (P ) of dynamic power and leakage power while the short-circuit power is negligible. The energy consumed by a computing task, that takes T seconds, is 2PT. A battery-operated 65nm digital CMOS device is found to consume equal amounts (P ) of dynamic power and leakage power while the short-circuit power is negligible. The energy consumed by a computing task, that takes T seconds, is 2PT. Compare two power reduction strategies for extending the battery life: Compare two power reduction strategies for extending the battery life: A.Clock frequency is reduced to half, keeping all other parameters constant. B.Supply voltage is reduced to half. This slows the gates down and forces the clock frequency to be lowered to half of its original (full voltage) value. Assume that leakage current is held unchanged by modifying the design of transistors.

8/22/06 and 8/24/06ELEC / Lecture 240 A. Clock Frequency Reduction Reducing the clock frequency will reduce dynamic power to P / 2, keep the static power the same as P, and double the execution time of the task. Reducing the clock frequency will reduce dynamic power to P / 2, keep the static power the same as P, and double the execution time of the task. Energy consumption for the task will be, Energy consumption for the task will be, Energy = (P / 2 + P ) 2T = 3PT which is greater than the original 2PT.

8/22/06 and 8/24/06ELEC / Lecture 241 B. Supply Voltage Reduction When the supply voltage and clock frequency are reduced to half their values, dynamic power is reduced to P / 8 and static power to P / 2. The time of task is doubled and the total energy consumption is, When the supply voltage and clock frequency are reduced to half their values, dynamic power is reduced to P / 8 and static power to P / 2. The time of task is doubled and the total energy consumption is, Energy = (P / 8 + P / 2) 2T = 5PT / 4 =1.25PT The voltage reduction strategy reduces energy consumption while a simple frequency reduction consumes more energy. The voltage reduction strategy reduces energy consumption while a simple frequency reduction consumes more energy.