1 Logic design of asynchronous circuits Part II: Logic synthesis from concurrent specifications

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits2 Outline Overview of the synthesis flow Specification State graph and next-state functions State encoding Implementability conditions Speed-independent circuit –Complex gates –C-element architecture

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits3 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits4 x y z x+ x- y+ y- z+ z- Signal Transition Graph (STG) x y z Specification

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits5 x y z x+ x- y+ y- z+ z- Token flow

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits6 x+ x- y+ y- z+ z- xyz 000 x+ 100 y+ z+ y x y+ z- 010 y- State graph

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits7 Next-state functions xyz 000 x+ 100 y+ z+ y x y+ z- 010 y-

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits8 x z y Gate netlist

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits9 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits10 VME bus Device LDS LDTACK D DSr DSw DTACK VME Bus Controller Data Transceiver Bus DSr LDS LDTACK D DTACK Read Cycle

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits11 STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits12 Choice: Read and Write cycles DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK-DTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits13 Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits14 Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits15 Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits16 Circuit synthesis Goal: –Derive a hazard-free circuit under a given delay model and mode of operation

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits17 Speed independence Delay model –Unbounded gate / environment delays –Certain wire delays shorter than certain paths in the circuit Conditions for implementability: –Consistency –Complete State Coding –Persistency

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits18 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits19 STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits20 Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits21 Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS (DSr, DTACK, LDTACK, LDS, D)

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits22 QR (LDS+) QR (LDS-) Excitation / Quiescent Regions ER (LDS+) ER (LDS-) LDS- LDS+ LDS-

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits23 Next-state function 0  1 LDS- LDS+ LDS- 1  0 0  0 1 

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits24 Karnaugh map for LDS DTACK DSr D LDTACK DTACK DSr D LDTACK LDS = 0 LDS = /1?

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits25 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits26 Concurrency reduction LDS- LDS+ LDS DSr+

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits27 Concurrency reduction LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits28 State encoding conflicts LDS- LDTACK- LDTACK+ LDS

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits29 Signal Insertion LDS- LDTACK- D- DSr- LDTACK+ LDS+ CSC- CSC

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits30 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits31 Complex-gate implementation

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits32 Implementability conditions Consistency –Rising and falling transitions of each signal alternate in any trace Complete state coding (CSC) –Next-state functions correctly defined Persistency –No event can be disabled by another event (unless they are both inputs)

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits33 Implementability conditions Consistency + CSC + persistency There exists a speed-independent circuit that implements the behavior of the STG (under the assumption that ay Boolean function can be implemented with one complex gate)

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits34 Persistency a- c+ b+b+ b+b+ a c b a c b is this a pulse ? Speed independence  glitch-free output behavior under any delay

a+ b+ c+ d+ a- b- d- a+ c-a a+ b+ c+ a- b- c- a+ c- a- d- d+

a+ b+ c+ a- b- c- a+ c- a- d- d+ ab cd ER(d+) ER(d-)

ab cd a+ b+ c+ a- b- c- a+ c- a- d- d+ Complex gate

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits38 Implementation with C elements C R S z  S+  z+  S-  R+  z-  R-  S (set) and R (reset) must be mutually exclusive S must cover ER(z+) and must not intersect ER(z-)  QR(z-) R must cover ER(z-) and must not intersect ER(z+)  QR(z+)

ab cd a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d

a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d but...

a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d Assume that R=ac has an unbounded delay Starting from state 0000 (R=1 and S=0): a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ; R+ disabled (potential glitch)

ab cd a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d Monotonic covers

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits43 C-based implementations C S R d C d a b c a b c d weak a c d generalized C elements (gC) weak

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits44 Speed-independent implementations Implementability conditions –Consistency –Complete state coding –Persistency Circuit architectures –Complex (hazard-free) gates –C elements with monotonic covers –...

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits45 Synthesis exercise y- z-w- y+x+ z+ x- w y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ Derive circuits for signals x and z (complex gates and monotonic covers)

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits46 Synthesis exercise y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ wx yz Signal x

ASPDAC / VLSI Tutorial on Logic Design of Asynchronous Circuits47 Synthesis exercise y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ wx yz Signal z