Power Optimization in Low-Voltage High-Speed High-Resolution Pipelined ADCs Hassan Sarbishaei Ehsan Zhian Tabasy Tahereh Kahookar Toosi Reza Lotfi {hsarbishaei, ezhian, tktoosi, Integrated Systems Lab. Dept. of Electrical Engineering, Ferdowsi University of Mashhad Mashhad, I.R.Iran August 2006

Low-Voltage High-speed Pipelined ADCs Power Optimization in High Resolution Sarbishaei, Zhian, Toosi, LotfiAugust Abstract ► LOW-POWER design of low-voltage high-speed high-resolution A/D converters is presented. By expressing the total current consumption of the ADC as well as the ADC noise power as functions of the stage resolutions, the stage capacitors and the compensation capacitors of the cascode-compensated opamps, all those parameters are optimally determined in order to minimize power consumption for a definite budget for the noise power. In this methodology, the small-signal settling is considered as well as the large-signal settling. Besides, the contribution of the comparators is considered in the entire ADC current consumption. At last two power-optimized pipelined ADCs utilizing the proposed and conventional design methods are presented and compared in 0.18µm CMOS technology with 1.2V supply voltage. Considerable reduction in power consumption is achieved.

Low-Voltage High-speed Pipelined ADCs Power Optimization in High Resolution Sarbishaei, Zhian, Toosi, LotfiAugust Power Optimum Compensation of Fast-Settling Opamps IiIi IcIc IaIa

Low-Voltage High-speed Pipelined ADCs Power Optimization in High Resolution Sarbishaei, Zhian, Toosi, LotfiAugust Pipeline Structure

Low-Voltage High-speed Pipelined ADCs Power Optimization in High Resolution Sarbishaei, Zhian, Toosi, LotfiAugust Proposed Methodology ► TOTAL input-referred noise can be stated as a function of opamp parameters, C F, C C and each stage resolution. These parameters should be chosen in a way that meets noise constraint (predefined SNR), while achieving minimum power consumption. ► USING an optimization program, e.g. MATLAB, the optimum values of these parameters can be found. Finally with the aid of a circuit simulator, e.g. HSPICE, the total ADC utilizing these parameters is simulated. Optimization Program HSPICE Desired SNR Optimized Circuit I i, C C, C F

Low-Voltage High-speed Pipelined ADCs Power Optimization in High Resolution Sarbishaei, Zhian, Toosi, LotfiAugust Dependency of Pdiss on ADC Parameters ►Pdiss vs. SNR ►Pdiss vs. Supply Voltage ►Pdiss vs. Sampling Rate

Low-Voltage High-speed Pipelined ADCs Power Optimization in High Resolution Sarbishaei, Zhian, Toosi, LotfiAugust Simulation Results Proposed Methodology Conventional Methodology Specification SNDR (dB) SFDR (dB) ENOB (bit) 3960Power Dissipation (mW) 1.2 V DD (V) 0.8 V FS (V) Stage #3Stage #2Stage #1Parameters 112 Effective Resolution (bit) 0.28 / / / 3.23 Unit / Compensation Capacitor (pF) (Proposed ADC) 1 / / 3.86 Unit / Comp. Capacitor (pF) (Conventional ADC)

Low-Voltage High-speed Pipelined ADCs Power Optimization in High Resolution Sarbishaei, Zhian, Toosi, LotfiAugust Conclusion ► AN effective yet simple and general design methodology for power optimization in pipelined ADCs is presented. The effectiveness of proposed method over conventional optimization methods is illustrated and finally, two design examples with the same ADC specifications are simulated using HSPICE to show the advantage of proposed method. Simulation results show about 33% decrease in total power consumption of proposed ADC design compared to exemplified conventional method.