RESYN'09 March 2009 Newcastle upon Tyne 1 Workcraft – a Framework for Interpreted Graph Models Ivan Poliakov, Arseniy Alekseyev, Victor Khomenko, Alex.

Slides:



Advertisements
Similar presentations
Comparison of Several Meta-modeling Tools 2 Yi Lu Computer Science Department McGill University
Advertisements

Andrey Mokhov, Victor Khomenko Danil Sokolov, Alex Yakovlev Dual-Rail Control Logic for Enhanced Circuit Robustness.
© Chinese University, CSE Dept. Software Engineering / Software Engineering Topic 1: Software Engineering: A Preview Your Name: ____________________.
1 BalsaOpt a tool for Balsa Synthesis Francisco Fernández-Nogueira, UPC (Spain) Josep Carmona, UPC (Spain)
Southampton: Oct 99AMULET3i - 1 AMULET3i - asynchronous SoC Steve Furber - n Agenda: AMULET3i Design tools Future problems.
1 Advanced Digital Design Synthesis of Control Circuits by A. Steininger and J. Lechner Vienna University of Technology.
Hazard-free logic synthesis and technology mapping I Jordi Cortadella Michael Kishinevsky Alex Kondratyev Luciano Lavagno Alex Yakovlev Univ. Politècnica.
ITEC810 Project Simulation for Verification of Business Collaboration Reliability Project Supervisor: Jian Yang Student: ZhengYang Wang,
Hardware and Petri nets Synthesis of asynchronous circuits from Signal Transition Graphs.
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT Victor Khomenko, Maciej Koutny, and Alex Yakovlev University.
12. Summary, Trends, Research. © O. Nierstrasz PS — Summary, Trends, Research Roadmap  Summary: —Trends in programming paradigms  Research:...
Detecting State Coding Conflicts in STGs Using Integer Programming Victor Khomenko, Maciej Koutny, and Alex Yakovlev University of Newcastle upon Tyne.
Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel.
VERTAF: An Application Framework for Design and Verification of Embedded Real-Time Software Pao-Ann Hsiung, Shang-Wei Lin, Chih-Hao Tseng, Trong-Yen Lee,
13. Summary, Trends, Research. © O. Nierstrasz PS — Summary, Trends, Research Summary, Trends, Research...  Summary: functional, logic and object-oriented.
Combining Decomposition and Unfolding for STG Synthesis (application paper) Victor Khomenko 1 and Mark Schaefer 2 1 School of Computing Science, Newcastle.
1 Logic synthesis from concurrent specifications Jordi Cortadella Universitat Politecnica de Catalunya Barcelona, Spain In collaboration with M. Kishinevsky,
ACSD Conference, Augsburg, Summer Flat Arbiters Andrey Mokhov 1, Victor Khomenko 2, Alex Yakovlev 1 1 School of Electrical, Electronic and Computer.
Visualisation and Resolution of Coding Conflicts in Asynchronous Circuit Design A. Madalinski, V. Khomenko, A. Bystrov and A. Yakovlev University of Newcastle.
Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction based on STG Unfoldings V. Khomenko, A. Madalinski and A. Yakovlev University.
STG-based synthesis and Petrify J. Cortadella (Univ. Politècnica Catalunya) Mike Kishinevsky (Intel Corporation) Alex Kondratyev (University of Aizu) Luciano.
Branching Processes of High-Level Petri Nets Victor Khomenko and Maciej Koutny University of Newcastle upon Tyne.
An Introduction to Synopsys Design Automation Jeremy Lee November 7, 2007.
UFO’07 26 June 2007 Siedlce 1 Use of Partial Orders for Analysis and Synthesis of Asynchronous Circuits Alex Yakovlev School of EECE University of Newcastle.
12. Summary, Trends, Research. © O. Nierstrasz PS — Summary, Trends, Research Roadmap  Summary: —Trends in programming paradigms  Research:...
Detecting State Coding Conflicts in STGs Using SAT Victor Khomenko, Maciej Koutny, and Alex Yakovlev University of Newcastle upon Tyne.
1 A Case for Using Signal Transition Graphs for Analysing and Refining Genetic Networks Richard Banks, Victor Khomenko and Jason Steggles School of Computing.
IS&T Scientific Visualization Tutorial – Spring 2010 Robert Putnam Plotting packages overview.
Automatic synthesis and verification of asynchronous interface controllers Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel.
Asynchronous Circuit Verification and Synthesis with Petri Nets J. Cortadella Universitat Politècnica de Catalunya, Barcelona Thanks to: Michael Kishinevsky.
Behavioural synthesis of asynchronous controllers: a case study with a self-timed communication channel Alex Yakovlev, Frank Burns, Alex Bystrov, Albert.
1 Chapter 7 Design Implementation. 2 Overview 3 Main Steps of an FPGA Design ’ s Implementation Design architecture Defining the structure, interface.
© 2008 IBM Corporation Behavioral Models for Software Development Andrei Kirshin, Dolev Dotan, Alan Hartman January 2008.
Component-based Authoring of Complex, Petri net-based Digital Library Infrastructure Yung Ah Park, Unmil P. Karadkar, and Richard Furuta Department of.
Basic Concepts The Unified Modeling Language (UML) SYSC System Analysis and Design.
DIVA. What Is Diva ? Diva is a software infrastructure for visualizing and interacting with dynamic information spaces. Visualizations are built by hooking.
Architecture Of ASP.NET. What is ASP?  Server-side scripting technology.  Files containing HTML and scripting code.  Access via HTTP requests.  Scripting.
ISE. Tatjana Petrovic 249/982/22 ISE software tools ISE is Xilinx software design tools that concentrate on delivering you the most productivity available.
Trigger design engineering tools. Data flow analysis Data flow analysis through the entire Trigger Processor allow us to refine the optimal architecture.
A Usable Reachability Analyser Victor Khomenko Newcastle University.
Chap. 1 Overview of Digital Design with Verilog. 2 Overview of Digital Design with Verilog HDL Evolution of computer aided digital circuit design Emergence.
UK Asynchronous Forum, September Synthesis of multiple rail phase encoding circuits Andrey Mokhov, Crescenzo D’Alessandro, Alex Yakovlev Microelectronics.
ASIC/FPGA design flow. FPGA Design Flow Detailed (RTL) Design Detailed (RTL) Design Ideas (Specifications) Design Ideas (Specifications) Device Programming.
Reliable Design of Safety Critical Systems Dr. Abhik Roychoudhury School of Computing
Khoros Yongqun He Dept. of Computer Science, Virginia Tech.
IBM Software Group ® Overview of SA and RSA Integration John Jessup June 1, 2012 Slides from Kevin Cornell December 2008 Have been reused in this presentation.
Selected Topics in Software Engineering - Distributed Software Development.
Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics.
H.G.Essel: Go4 - J. Adamczewski, M. Al-Turany, D. Bertini, H.G.Essel, S.Linev CHEP 2003 GSI Online Offline Object Oriented Go4.
Tools, Formats, & Solutions.  Survey of literature found 3 interesting ways Petri Nets are used  BioPNML – Petri Nets for Bio  GJobDL – Petri Nets.
ReNeW Reference Net Workshop Presenter Yao Sun. The ReNeW Features  High-level Petri Nets (Support Predicate)  Place/Transition Nets  Petri Nets with.
Java 3D Web Apps and Services. Presentation Overview l Java3D Overview l Software l Java3D API l Scene Graph Programming Model l Java3D Terminology l.
1 Copyright  2001 Pao-Ann Hsiung SW HW Module Outline l Introduction l Unified HW/SW Representations l HW/SW Partitioning Techniques l Integrated HW/SW.
H.G.Essel: Go4 - J. Adamczewski, M. Al-Turany, D. Bertini, H.G.Essel, S.Linev ROOT 2002 GSI Online Offline Object Oriented Go4.
August 2003 At A Glance The IRC is a platform independent, extensible, and adaptive framework that provides robust, interactive, and distributed control.
ProShell Procedure Framework Status MedAustron Control System Week 2 October 7 th, 2010 Roland Moser PR a-RMO, October 7 th, 2010 Roland Moser 1.
STAR Webinars Ontology driven diagram generator for health simulation models Andrew Sutcliffe.
A new GreatSPN GUI for GSPN editing and CSL TA model checking Tool presentation Elvio G. Amparore UNIVERSITÀ DEGLI STUDI DI TORINO.
Gerhard Dueck -- CS3013Analysis 1. Gerhard Dueck -- CS3013Analysis 2 Why analysis?  Yield a more precise specification of the requirements.  Introduce.
ASIC/FPGA design flow. Design Flow Detailed Design Detailed Design Ideas Design Ideas Device Programming Device Programming Timing Simulation Timing Simulation.
Université Toulouse I 1 CADUI' June FUNDP Namur Implementation Techniques for Petri Net Based Specifications of Human-Computer Dialogues.
Specification mining for asynchronous controllers Javier de San Pedro† Thomas Bourgeat ‡ Jordi Cortadella† † Universitat Politecnica de Catalunya ‡ Massachusetts.
EECE 320 L8: Combinational Logic design Principles 1Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 8: Combinational Logic Design Principles.
Go4 v2.2 Status & Overview CHEP 2003
Victor Khomenko Newcastle University
Asynchronous Interface Specification, Analysis and Synthesis
Andrey Mokhov, Jordi Cortadella, Alessandro de Gennaro
Raspberry Pi Stefan konzelmann
AIMS Equipment & Automation monitoring solution
Synthesis of multiple rail phase encoding circuits
Presentation transcript:

RESYN'09 March 2009 Newcastle upon Tyne 1 Workcraft – a Framework for Interpreted Graph Models Ivan Poliakov, Arseniy Alekseyev, Victor Khomenko, Alex Yakovlev

RESYN'09 March 2009 Newcastle upon Tyne 2 Interpreted Graph Models Static graph structure –Nodes –Arcs Additional entities –Tokens –Node states –Arc states –Etc Examples: –Petri Nets –Static Data Flow Structures –Gate-level circuits

RESYN'09 March 2009 Newcastle upon Tyne 3 Petri Nets as a low-level 'language' Many high-level models do not have sufficiently developed theory and associated tools Petri Nets have exensive theory and many efficient tools Approach: convert high-level models into PNs for analysis/verification

RESYN'09 March 2009 Newcastle upon Tyne 4 Verification workflow

RESYN'09 March 2009 Newcastle upon Tyne 5 Workcraft A tool for working with IGMs –Visual editing –Interactive simulation –Automated verification For researchers: –define new Interpreted Graph Models –inherit visual editing and simulation features of the framework For system designers –a consistent framework for different formalisms –convenient analysis and verification functions

RESYN'09 March 2009 Newcastle upon Tyne 6 Workcraft GUI overview

RESYN'09 March 2009 Newcastle upon Tyne 7 Working with models Creating new model

RESYN'09 March 2009 Newcastle upon Tyne 8 Working with models Simulation Modes: –Automatic –Interactive –Trace-replay Step-by-step

RESYN'09 March 2009 Newcastle upon Tyne 9 Model interoperability

RESYN'09 March 2009 Newcastle upon Tyne 10 More complex interoperability

RESYN'09 March 2009 Newcastle upon Tyne 11 Use case — Static Data Flow Verification Original state Deadlock state 29 steps

RESYN'09 March 2009 Newcastle upon Tyne 12 Use case — Asynchronous circuit verification Hazard caused by wire delay

RESYN'09 March 2009 Newcastle upon Tyne 13 Summary Workcraft is a framework for Interpreted Graph Models –Provides visual editing and simulation features –Provides automated verification features Workcraft has been used in several real-life cases –SDFS verification –Circuit verification (e.g. the design of a multiresource arbiter by Golubcovs et al.) –CPOG-based synthesis Available free for academic use at –async.org.uk/workcraft

RESYN'09 March 2009 Newcastle upon Tyne Workcraft 2 Almost complete rewrite of Workcraft 1: No longer OpenGL dependent – visualisation engine switched from custom-written to Java2D – much better portability Customisable multi-window interface – Persistent docking layout – Hideable utility windows

RESYN'09 March 2009 Newcastle upon Tyne Workcraft 2 (cont.) Logical model data and visual data are separate – Logical models can exist without visual data – Import from files without visual data is allowed (such as.g) – Visual data can be attached on-the-fly Console mode – JavaScript-based command line – Scriptable batch processing

RESYN'09 March 2009 Newcastle upon Tyne 16 Use case – Balsa circuit re-synthesys –Visualisation of Balsa net-lists –Generation of STGs for individual HS components –STG composition of the entire HS circuit

RESYN'09 March 2009 Newcastle upon Tyne 17 Individual component STGs "SequenceOptimised" component STG "Concur" component STG

RESYN'09 March 2009 Newcastle upon Tyne 18 Resulting STG composition activate out0 out1 out2 out3

RESYN'09 March 2009 Newcastle upon Tyne (tool demo)