Combinational Logic Design Sections 3-1, 3-2 Mano/Kime

Combinational Logic Design Hierarchy Top-Down Design Computer-Aided Design –Hardware Description Languages VHDL Verilog –Logic Synthesis Combinational Logic Circuits –Multiplexers –Binary Adders –Binary Subtractions –Shifters –Comparators –Decoders and Encoders

Combinational vs. Sequential Circuits Combinational Circuit n-inputsm-outputs (Depend only on inputs) Combinational Circuit Inputs Outputs Storage Elements Next state Present state Sequential Circuit Combinational Circuit

Design Hierarchy

Top-Down Design Top-Down Bottom-Up Physical/Geometry Structural Behavioral Processor Hardware Modules ALUs, Registers Gates, FFs Transistors Systems Algorithms Register Transfer Logic Transfer Functions Architectural Algorithmic Functional Block Logic Circuit Rectangles Cell, Module Plans Floor Plans Clusters Physical Partitions Gajski and Kuhn’s Y Chart

Computer-Aided Design Schematic Capture Hardware Description Languages –CUPL, ABEL –VHDL, Verilog Logic Simulation Logic Synthesis

VHDL VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE standard specification language (IEEE ) for describing digital hardware used by industry worldwide VHDL enables hardware modeling from the gate level to the system level

VHDL’s History Very High Speed Integrated Circuit (VHSIC) Program –Launched in 1980 –Aggressive effort to advance state of the art –Object was to achieve significant gains in VLSI technology –Need for common descriptive language –$17 Million for direct VHDL development –$16 Million for VHDL design tools Woods Hole Workshop –Held in June 1981 in Massachusetts –Discussion of VHSIC goals –Comprised of members of industry, government, and academia

VHDL’s History (Cont.) In July 1983, a team of Intermetrics, IBM and Texas Instruments were awarded a contract to develop VHDL In August 1985, the final version of the language under government contract was released: VHDL Version 7.2 In December 1987, VHDL became IEEE Standard and in 1988 an ANSI standard In September 1993, VHDL was restandardized to clarify and enhance the language VHDL has been accepted as a Draft International Standard by the IEC

Additional Benefits of VHDL Allows for various design methodologies Provides technology independence Describes a wide variety of digital hardware Eases communication through standard language Allows for better design management Provides a flexible design language Has given rise to derivative standards : –WAVES, VITAL, Analog VHDL

High-Level Flow for Logic Synthesis Tool

Combinational Logic Circuits Multiplexers Binary Adders Binary Subtractions Shifters Comparators Code Converters Decoders and Encoders