LoopBuster Hardware Loop Detection in Fast Mesh Ethernet Networks Uriel Peled and Tal Kol Guided by Boaz Mizrahi Advised by Gideon Kaempfer Digital Systems Laboratory Faculty of Electrical Engineering, Technion Winter 2007 – Spring 2009

LoopBuster Stop Loops Without Tree Topology A B C New Hardware Device: “LoopBuster” Improved Switches: Changed Learning Improved Switches: Changed Learning Mesh Topology: Loops Allowed!

Abstract Ethernet relies on Spanning Tree to assure loop- free topology Inefficient in terms of throughput, latency LoopBuster allows mesh topologies in Ethernet LoopBuster hardware device, modified switches Patent-pending LoopBuster filtering algorithm Multi-stage filtering for memory efficiency Empirical / theoretical analysis of algorithm parameters Verilog implementation of LoopBuster on Xilinx Virtex 2 Pro (Memec board)

Network Simulation in Software Minimal HW (1PC), C++, SW Timeline Real-world rates, real-world traffic Based on a genetic algorithm Genetic representation: filter size list ( 13,12,10,10,9,9,8,8,7,7,6) Improve a pre-defined fitness function False positives over real traffic + Total memory size Two-stage mutation General (add/remove filter, change filter size, switch filters) Specific (num filters, size of largest, create descending chain) Algorithm Analysis Empirical Param Selection

Architecture General Block Diagram

Architecture Board Block Diagram