Ensuring Correctness of Analog Circuits Using Pattern Matching Rajeev Narayanan, Alaeddine Daghar, Mohamed H. Zaki, and Sofiène Tahar Hardware Verification Group, Dept. Of ECE, Concordia University, Montreal, Canada

2 FAC 2011 Motivation Inheritance / Interactive Noise Non- Linearity Infinite State Space Technology Variation Combination of traditional and new verification strategies are needed Analog Design

3 FAC 2011 Outline Simulation Based Methods Pattern Matching  Longest Common Subsequence (LCS)  Longest Closest Subsequence (LCSS) Proposed Methodology Applications  Colpitts Oscillator  Rambus Ring Oscillator Conclusion and Future Work

4 FAC 2011 State of the Art - Simulation Behavioral LevelCircuit Level Statistical Modeling + Monte-Carlo Simulation Pros: Easy to Integrate Fast Cons: Defining Complex Monitors Accuracy of the Behavioral Model Pros: Accurate Technology Aware Cons: Simulation Run-Times Difficult to Automate

5 FAC 2011 Question? For different Monte-Carlo trials, if the simulation of the non-ideal circuit follows the output of an ideal circuit for say 99.0% and violates just 1.0% of the simulation time, ``Does the designer have to reject the circuit entirely?'' Pattern Matching Algorithm # of Closely Matched Sequence

6 FAC 2011 Longest Common Subsequence (LCS) Given two sequences X[1..m] and Y[1..n], find a longest subsequence that is common to X and Y. BCBA = LCS(X,Y) Run Time = O(n*2^m) ABCBDABABCBDAB BDCABABDCABA X(1:m) m= 7 Y(1:n) n= 6 One-to-One Mapping  One-to-One mapping is NOT possible for Analog Circuits  Closely Matching Sequence for a given tolerance level Longest Closest Subsequence (LCSS)

7 FAC 2011 Longest Closest Subsequence (LCSS) LCSS(X, Y) Brute-Force Method Recursive Method Computing the Length of LCSS Optimal Path Finder  If ≤ ( +p) and ≥ ( -p), then is an LCSS of and  If ≠, then, if Z k ≠ X m, then is an LCSS of -1 and  If ≠, then, if Z k ≠ Y n, then is an LCSS of and -1 C[i,j] = C[i-1, j-1] + 1; ( X -p) ≤ Y ≤ ( X +p) max{C[i, j-1], C[i-1, j]}; otherwise Worst-Case Run-Time = O(nm)

8 FAC 2011 Example – Chuas Circuit  Matching Percentage: 81.2%  Run-Time Brute-Force: 1.01 sec Recursive: 0.49 sec  LCSS perform “Set-by-Set” matching rather than “Value-by-Value” basis (Advantage during Monte Carlo Simulation)  Efficient with offsets and signal with different origins

9 FAC 2011 Dealing with Offset Conditions Start-up Delay Time  Drift in Time Axis  Ex: PLL Lock Time Horizontal Offset  Shift of the entire signal  Ex: Jitter Period Question: How to verify such circuits that have offsets? Or Can we detect these offsets automatically?

10 FAC 2011 Proposed Methodology

11 FAC 2011 LCSS Based Offset Detection

12 FAC 2011 Application – Colpitts Oscillator  Voltage divider made by C 1 and C 2 causes oscillation  L, C 1 and C 2 determine the frequency of oscillation

13 FAC 2011 LCSS Computational Results One ideal and Seven different Colpitts Oscillator Circuit Monte-Carlo Simulation of 1000 trials

14 FAC 2011 Rambus Ring Oscillator Greenstreet et.al, Question: What is the probability that the circuit will have the fastest start-up delay time and what is the “trade-off”? (Needed for PLL!!!)

15 FAC 2011 Parametric Analysis  Sweep “r” and initial condition  Components Values are fixed at a given time  Not realistic – Follow MonteCarlo Simulation Initial Condition = 1V

16 FAC 2011 MonteCarlo Simulation  M = 100 trials

17 FAC 2011 What is the Trade-off?  38 out of 100 circuits have 67% matching and has fastest start-up delay time (Initial Condition - 1V)

18 FAC 2011 Conclusion and Future Work  Methodology based on pattern matching for analog circuits  LCSS based on variable simulation step-size  Frequency Offsets  Hypothesis Testing hvg.ece.concordia.ca