Computer Architecture Lecture 5 Design Decisions for a 64-bit RISC Architecture Source of almost all Slide: Text Book

Addressing Modes

Summery of use of memory addressing mode Displacement 10%20%30%40%50% Frequency of the addressing mode 0% Tex Spice gcc Tex Spice gcc Tex Spice gcc Tex Spice gcc 1% 6% 1% 16% 6% 24% 3% 11% 17% 43% 39% 32% 55% 40% Memory indirect Scaled Register Indirect Immediate Summary of Memory Addressing Mode 75% to 90 %

Size of Displacement Number of Bits needed for Displacement Percentage of Displacement 0% 5% 10% 15% 20% 25% 30% 35% 40% 45% bit Displacement field will capture 75% to 99%

Use of Immediate Operand

Immediate Addressing Mode- Displacement distribution Number of Bits needed for Immediate Operand Percentage of Immediate 0% 5% 10% 15% 20% 25% 30% 35% 40% 45% bit Displacement field will capture 50% to 80%

Distribution by benchmark size Double Word (64 bits) Word (32 bits) 10%20%30%40%50% 0%Half word (16bits) Byte (8bits) 70% 59% 29% 26% 5% 1% 10% Distribution of Data Accesses by Size for Benchmark Program 60%70%80% Floating point average Integer average

Instruction Types

Instruction Type Frequency RANK80x86 on SPEC95Percentage 1Load22 2Conditional Branch20 3Compare16 4Store12 5Add8 6And6 7Sub5 8Move R to R4 9Call, Return2 TOTAL = 96%

Instructions for Control Flow The Measurements of branch and jump behavior are fairly independent of other measurements and applications. Four types of control flow change: Conditional branches Jumps Procedure calls Procedure returns

Three classes of control flow instructions Conditional Branch 100% Call/return Jump 25%50% 8% 19% 10% 6% 82% 75% Control Flow instructions into three classes 75% Floating point average Integer average

Types of compares in conditional branching Less than Greater than or equal 10%50% 0% 44% 33% 34% 35% Frequency of Comparison Types in Branches Floating point average Integer average 20%30%40% Less than or equal Equal Not Equal5% 2% 16% 18% 0% 11% Greater than

Branch distances in terms of number of instructions

Conditional branch options Conditional Code (CC) register E.g. 80x86,ARM etc. Tests special bit set by ALU operations Advantage Sometimes condition is set free Disadvantage CC is extra state. Condition codes constrain the ordering of instructions since they pass information from one instruction to a branch

Conditional branch options Conditional Register E.g. Alpha, MIPS Tests arbitrary register with the result of a comparison Advantage Simple Disadvantage Uses up register

Conditional branch options Compare and branch E.g. PA-RISC, VAX Compare is part of the branch. Often compare is limited to subset Advantage One instruction rather than two for a branch Disadvantage May be too much work per instruction for pipelined execution

Summary of Analysis FeatureSet Included Use Frequency Comments Data Size64-bitUpto 70% Addressing ModeRegister Indirect, Displacement, Imm 75% to 95% Size of Displacement 16-bit75% to 99% Size of Imm16-bit50% to 80% Size of Branch Offset 16-bitabout 99%75% branches are in forward direction Types of ALU OpsLoad/Store, Cond. Branch etc 96%Refer earlier slide Branch CondtionEq, Not Eq, <, <=

Encoding an instruction set

Basic Blocks of a Processor Memory Model Memory Address N-bit Data In M- Bits Data Out M-bits Read/Write Basic Memory Operations Read/Load : Regs[Rx]  Mem[Address] Write/Store: Mem[Address]  Regs[Rx] Effective Address: Imm: Address =Imm Displacement: Address = Imm + Regs[Ra] Indirect: Address = Regs[Ra]

Datapath or ALU Model A Operand B Operand AluOut ALU Basic ALU Operations 1. AluOut = A op B 2. AluOut = A op Imm 3. Aluout = Shifted A by Shamt (Shift Amount), B is Ignored A, B and AluOut are same size (32 or 64-bit) What is the size of shamt? What is the size of AluOp? AluOp Shamt Some Conditions Or IMM

Register File A Field ?- bit A data Out M-bits Register Write B Field ?- bit Write Field ?-bit B Data Out M-bits Basic Register File Operations 1. A = Regs[A field] 2. B = Regs[B field] 3. Regs[Write field] = Write Data if Register Write =1 Write Data