Space vs. Speed: Binary Adders 11.3 Space vs. Speed

Binary Adders VHDL Adder Carry Lookahead Adder

4-Bit Adder C A B S

Adder in VHDL entity adder is port ( a: in STD_LOGIC_VECTOR (3 downto 0); b: in STD_LOGIC_VECTOR (3 downto 0); sum: out STD_LOGIC_VECTOR (3 downto 0); carry: out STD_LOGIC ); end adder;

std_logic_arith.vhd

CiCi AiBiAiBi C i+1 C i+1 = A i & B i # C i & B i # C i & A i

std_logic_unsigned.vhd

adder.vhd

Binary Multiplier Half Adders are Sufficient Since there is no Carry-in in addition to the two inputs to sum 2 bit by 2 bit

Binary Multiplier 4 bit by 3 bit yields 7 bit result

Binary Adders VHLD Adder Carry Lookahead Adder

C 2 = G 1 + P 1 (G 0 + P 0 C 0 ) = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 (G 1 + P 1 (G 0 + P 0 C 0 )) = G 2 + P 2 (G 1 + P 1 G 0 + P 0 C 0 ) = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P l P 0 C 0 G 0-3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P l G 0 P 0-3 = P 3 P 2 P l P 0

Ripple Carry Adder (4-bit)

Typically, longest delay path through n-bit ripple carry adder is 2n + 2 Tends to be one of the largest delays in a typical computer design Counts as 2 gate delays

Gate Delays 16-bit Adder Gate Delays 64-bit Adder Gate Delays

Carry Lookahead Adder Uses Propogate and Generate signals to “lookahead” for incoming carry signals More complicated hardware configuration Substantial decrease in gate delays

PFA: Partial Full Adders Ripple Carry Carry Lookahead

Propagate P = A xor B If P = ‘1’ then the carry is “propagated” through. If P = ‘0’ then the carry is not “propagated” through. Generate G = A and B If G = ‘1’ a carry is “generated” regardless of the carry bit.

C in A B C out S PGPG For final carry determination, the Propagate signal is ANDed with the Carry Out and the Generate signal is ORed to the resulting signal. GPC in C out

Always Generate a Carry for A = 1, B = 0 C in A B C out S PGPG C in A B C out S PGPG Propagate the Carry in

C out

PFA For Bit # 1

Bit #1 Bit #2 Bit #3 Bit #4 1 4

Significant Delay Reduction 4 - bit Ripple: 10 Delays CLA:6 Delays 1 CLA level: 1*4 + 2 = bit Ripple:34 Delays CLA: 10 Delays 2 CLA levels: 2*4 + 2 = bit Ripple:130 Delays CLA:14 Delays 3 CLA levels: 3*4 + 2 = 14 But at the expense of a significant increase in the number of gates used by the circuit