CSE 140L Lecture 4 Flip-Flops, Shifters and Counters Professor CK Cheng CSE Dept. UC San Diego

1)F-F 2)Shift register 3)Counter (Asynchronous) 4)Counter (Synchronous)

Flip-Flops DFF D CE C CLR Q CLR CE D C Q 1 X X X X X No change Asynchronous Clear Inputs Output Clock Enable CLK = 0 CLK = 1

D Q CLK t t t t setup t hold D Q tcqtcq D-FF Timing

Input Timing Constraints Setup time: t setup = time before the clock edge that data must be stable (i.e. not changing) Hold time: t hold = time after the clock edge that data must be stable Aperture time: t a = time around clock edge that data must be stable (t a = t setup + t hold )

Output Timing Constraints Propagation delay: t pcq = time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing) Contamination delay: t ccq = time after clock edge that Q might be unstable (i.e., start changing)

Setup Time Constraint The setup time constraint: The maximum delay from register R1 through the combinational logic. The input to register R2 must be stable at least t setup before the clock edge. T c ≥ t pcq + t pd + t setup t pd ≤ T c – (t pcq + t setup )

Hold Time Constraint The hold time constraint depends on the minimum delay from register R1 through the combinational logic. The input to register R2 must be stable for at least t hold after the clock edge. t hold < t ccq + t cd t cd > t hold - t ccq

2) A 3 Bit Shift Register D Q CLK D Q D Q 0 0 X X X 11 0 X X X Time Steps A B C D A B C D Signal A is given as input.

3) A 3 Bit Counter (Asynchronous) T Q CLK T Q T Q t A C B t t B C t A Reset A(0) = B(0) = C(0) = Time C B A