TinyOS Meets Silicon Jason Hill NEST Retreat Summer 2002

Breaking Out COTS hardware has brought us this far but… Next step is custom silicon Like it or not, our platform progress is tied to hardware/silicon design cycle times Silicon give us: Size Cost Performance

Talk Outline Design History First Attempt at Silicon Chip results Second generation design Next Steps

Design Lineage COTS dust prototypes (Kris Pister et al.) weC Mote (30 produced) Rene Mote (850 produced) Dot (1000 produce) Mica node (current, 1800 produced) Time warp accelerator for MICA Silicon prototype ?

First Silicon Goals Continue trend of building and evaluating Goal is to build something to get momentum Learn “economics of silicon” RF Accelerator designed as mica add-on Increase RF transmission speed and reliability while decreasing CPU involvement

Capabilities RF Communication Support Start Symbol Detection Signal clock extraction and continual resynchronization Transmission and reception buffering to relax CPU real-time constraints Energy Consumption 1 Mbps (> 100 uA) Mote Requires approximately 3mA of CPU.

“Mote Chip” Goals Replicate and extend the functionality of the MICA Decrease size of node to cubic millimeters Reduce cost to <$1 Include AVR-like* Core, ADC, RF Communication Support, UART, SPI, RAM, Radio, Timing modules Target shortcoming of COTS capabilities

Experimental Platform Silicon is hard and expensive Designs must be correct the first time Simulation is nice but very time consuming FPGAs provide essential hardware debugging mechanism

Mode Chip experimental setup Xilinx XCV2000E 2.5 million gates – 10x the size of an AVR core Also has… Ethernet A/V Encoder Compact Flash Internal and External RAM

Silicon TinyOS Support

Communication Interface Hardware provides ‘AM’ interface Same functionality originally implemented in hardware Hardware handles Message send command with TOSMsgPtr Hardware signals Message arrival event with TOSMsgPtr CPU communication overhead dropped from approx. 2MIPS down to 0.

First Prototype IO Pads RAM blocks MMU logic Debug logic ADC CPU Core RF Place Holder 2mm Core Area only 50% full…

Chip Area Breakdown 3K RAM = 1.5 mm 2 CPU Core = 1mm 2 RF COMM stack =.5mm 2 RADIO =.25 mm 2 ADC 1/64 mm 2 I/O PADS

Core Area Breakdown

External Components Required Current Prototype 2 External clock generators 1 External radio Power source End Goal 1 External Inductor (RF oscillation) 1 External Crystal (time keeping) Power source

Conclusion Custom Silicon is available to us Silicon helps with size, performance, and cost 4mm 2 Mote Chip prototype is due back August 1 Full mote chip to be sent out November ‘02