NETWORK ON CHIP ROUTER Students : Itzik Ben - shushan Jonathan Silber Instructor : Isaschar Walter Characterization presentation Winter 2006

Problem : power, size and performance not practical for multi-processor chips using a single bus interconnection. Solution : Network on Chip, based interconnection: fast, reliable data and low power consumption.

 Implement a router for NoC in VHDL based upon research made by faculty members.  Design and implement global interface units between NoC routers and process units.  Design and implement an application of multi processing units using a Network on Chip based interconnection. Project goals

General Schematic ROUTER Interface Process Unit Process Unit Process Unit Process Unit Process Unit Process Unit ROUTER Interface ROUTER Interface ROUTER Interface ROUTER Interface ROUTER Interface NoC

Interface Process Unit Process Unit Process Unit Process Unit Process Unit Process Unit Interface to Router Packets in Wormhole architecture From comm. to Packets To Router

Router ROUTER Routing By packet Wormhole Virtual-Channel

Project schedule - First Semester Goals  Get familiar with working environment (board EDK & HDL designer). (weeks 2-6)  Operate the Virtex II Pro board including FPGA and peripherals. (weeks 6-9)  Design and implementing a simple router. (weeks 10-14)

Project schedule - Second Semester Goals  Development of interface to the network.  Implement a QNoC based application on a FPGA.