1 Clockless Logic Montek Singh Tue, Mar 16, 2004

2Outline  Where are we?  Recap: Logic Gate Families  New Topic: Asynchronous Pipelined Processing

3 Where are we? Introduction to clockless logic Introduction to clockless logic  Benefits and challenges  Data representation, and control signaling Graphical representation of asynchronous systems Graphical representation of asynchronous systems  Petri nets, state transition graphs, burst-mode machines, etc. Algorithms for logic synthesis Algorithms for logic synthesis  Combinational & Sequential VLSI design primer VLSI design primer  Design techniques  High-performance: fine-grain pipelining  Low-power Formal methods Formal methods  Performance analysis  Verification Case studies of real-world asynchronous processors Case studies of real-world asynchronous processors

4 Review: Logic Gate Families  Static CMOS logic  Dynamic logic, or “domino” logic  Transmission gates, or “pass-transistor” logic

5 Static CMOS logic Advantages: output always strongly driven output always strongly driven  pull-up and pull-down networks are fully-complementary; exactly one of them is “on” always  good immunity from noise and leakage both inverting and non-inverting functions implementable both inverting and non-inverting functions implementable  each gate is inverting  cascade two gates together to get non-inverting logic Disadvantages: slow/big PMOS devices needed (in addition to NMOS) slow/big PMOS devices needed (in addition to NMOS)  greater chip area  higher power consumption  slower switching speed

6 Dynamic Logic, or “domino” Key idea: only use NMOS’s to compute function only use NMOS’s to compute function use a single PMOS to reset use a single PMOS to resetAdvantages: significantly fewer transistors  smaller chip area significantly fewer transistors  smaller chip area higher speed, lower power higher speed, lower power  less “loading” on wires (drive fewer transistors) for async: no storage elements needed for async: no storage elements neededDisadvantages: need extra control input to precharge need extra control input to precharge logic is typically non-inverting only logic is typically non-inverting only more vulnerable to noise and leakage effects more vulnerable to noise and leakage effects

7 Dynamic Logic, or “domino” (contd.) Gate has 2 phases: precharge (=reset): output reset to ‘0’ precharge (=reset): output reset to ‘0’ evaluate: output computed  either stays ‘0’, or switches to ‘1’ evaluate: output computed  either stays ‘0’, or switches to ‘1’ Pull-up and pull-down must never both be simultaneously active: ensure that data inputs are reset while gate is precharging ensure that data inputs are reset while gate is precharging or, add a “footer” device or, add a “footer” device pull-downnetwork controls “evaluation” controls “precharge” PC data inputs control input data output pull-up network PC =0 ( asserted )  precharge PC =0 ( asserted )  precharge PC =1 ( de-asserted )  evaluate PC =1 ( de-asserted )  evaluate

8 Transmission Gates Key Idea: transistors used in a different configuration transistors used in a different configuration when switched on: instead of connecting output to Vdd or Gnd, they connect output to the input when switched on: instead of connecting output to Vdd or Gnd, they connect output to the inputAdvantage: very efficient for implementing switches and multiplexers very efficient for implementing switches and multiplexersDisadvantage: signal degradation unless both NFET and PFET passgates are used in a complementary configuration signal degradation unless both NFET and PFET passgates are used in a complementary configuration

9 Asynchronous Pipelined Processing  Pipelining basics  Fine-grain pipelining  Approach I: MOUSETRAP pipelines

10 A “coarse-grain” pipeline (e.g. simple processor) A “fine-grain” pipeline (e.g. pipelined adder) fetchdecodeexecute Background: Pipelining What is Pipelining?: Breaking up a complex operation on a stream of data into simpler sequential operations Performance Impact: + Throughput: significantly increased ( #data items processed/second) – Latency: somewhat degraded ( #seconds from input to output) Storage elements (latches/registers)

11 Focus of Asynchronous Community Our Focus: Extremely fine-grain pipelines “gate-level” pipelining = use narrowest possible stages “gate-level” pipelining = use narrowest possible stages each stage consists of only a single level of logic gates each stage consists of only a single level of logic gates  some of the fastest existing digital pipelines to date Application areas: general-purpose microprocessors general-purpose microprocessors  instruction pipelines: often stages multimedia hardware (graphics accelerators, video DSP’s, …) multimedia hardware (graphics accelerators, video DSP’s, …)  naturally pipelined systems, throughput is critical; input “bursty” optical networking optical networking  serializing/deserializing FIFO’s string matching? string matching?  KMP style string matching: variable skip lengths