REDUCED POWER SHIFT REGISTER WITH MULTIPHASE CLOCKS ELEC 6270 Kannan Govindasamy.

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Presentation transcript:

REDUCED POWER SHIFT REGISTER WITH MULTIPHASE CLOCKS ELEC 6270 Kannan Govindasamy

OUTLINE Objective Simulation Specification Background information ImplementationResultsConclusion

OBJECTIVE Design and Verify a 32 bit Shift Register with Multi-phase Clocks Study Low Voltage Power and Delay characteristics

Simulation Specification TechnologyTsmc035 Rated Voltage 5v NMOS Vth.54v PMOS Vth -.64V Temperature 27 C Degree Simulator ELDO ver

Background Information Dynamic Signal transitions Signal transitions Logic activity Glitches Short-circuit Short-circuitStatic Leakage Leakage

Shift Registers with Multiphase clocks

Multiphase Clock Generators Modified Johnson counter is used for Multiphase Clock generation

ELDO SIMULATION

Results Power Table N=1 Voltage Avg Power ObservedTheoreticalPower mW mW3.034mW uW1.24mW uW337.2uW uw270.4uW

Results Power Table N=4 Voltage Avg Power ObservedTheoreticalPower 55.08mW mW1.828mW uW812.8uW uW203.6uW uw164.5uW

Results Delay Table for N=1 VoltageDelay Observed (ns) Delay Calculated (ns)

Power vs Voltage

Delay vs Voltage Plot

Power-Delay Plot

Power Consumption vs Parallelism Degree of Parallelism Freq Power (mW) 1100MHz MHz MHz MHz MHz4.71

Summary A power reduction of 39.1% is achieved when degree of parallelism is 4. A power reduction of 45.07% is achieved for N=8. for further parallelism power reduction gets stabilized

Reference ELEC 6270 class slides by Dr.Agrawal Tsung-chu Huang, Kuen-Jong Lee, A Low-Power LFSR Architecture, Test symposium 2001