Hybrid Status Carl Haber 12-Aug-2008 UCSC

6 x 3 cm, 6 chips wide 10 x 10 cm, 10 chips wide 1 meter, 3 cm strip, 30 segments/side 192 Watts (ABCD chip), ~2.4 % Xo + support structure 1.2 meter, 2.5 cm strip, 48 segments/side ~ Watts W/chip) 1.7 – 2.4 % Xo + support structure, depends upon coolant and hybrid design Stave-07 Stave cm, 9 cm strip, 6 segments/side Stave-08 Prototypes and Designs

Intro We have developed a 6 chip ceramic ABCD hybrid for the Stave-2007 program –In use for ongoing studies of stave and transmission A new flex version of this will be fabricated as well. Layout complete, check prints –This will used to test substrate issues (PM talk) Beyond this a hybrid series is needed for the ABC-Next and Stave-2008 program Liverpool will lead this program July I met with the Liverpool and Oxford groups, in the UK, to discuss this program –Includes hybrid development and data transmission studies

flex ceramic

Ongoing Program More in PM talk Individual hybrids/modules work well electrically Main issue has been data transmission on the stave with multiple modules. Lack of robust response to LVDS commands Significant work on test bench with D.Nelson (many thanks for this…) While we have made a number of improvements we are not there yet This has delayed further mounting of modules on Stave-2007

Hybrid for Stave-2008, ABC-next Oxford Meeting July 30-31, 2008 –Phil Allport, Ashley Greenal, Tony Affolder, CH, Richard Nickerson, Tony Weidberg, Todd Huffman, Peter Phillips, Mike Tyndel A key issue has been how to accommodate robust early testing of the ABC-next and Stave- 2008, considering the lack of a MCC Drive towards a minimum area design Concern for data transmission problems –Parallel bus testing program Follow-up meeting in US, late Sept, proposed

Conclusion of Meeting A plan was developed to systematically address these various needs Liverpool will under take the design and fabrication of a series of hybrids over the next 6-9 months Various design choices will be made as options are understand further.

Proposal Hybrid-1: for ABC-next test in legacy mode. –Can 20 ABC-next operate as a system? –Not compatible with stave and bus cable –Large connector, control with modified Mustard –Interface to various powering options –To be ready this Fall along with ABC-next

Proposal A single PCB which can accommodate 2 hybrid fingers (with sensor) All module connections to PCB made using wire bonds (as done by US) Fusing current for 25µm Al wire is ~500mA Topology of connections will be similar to that presently used on US Stave Power/DCS towards one end and Data I/O at the opposite end of hybrid For module readout & configuration make use of SCTDAQ (Mustard+SLOG+LV3) Requires ABCns to operate in Legacy Mode (1 x Master/column) with data rate limited to 40MHz Mustard firmware will be modified to accept increased ChipID field AC-coupled LVDS data transmission to/from module LVDS RX (CLK, COM, etc.) powered parasitically off module VDD (2V5) LVDS TX (Module data) powered from LV3 power supply VDD (4V) Make use of plug-in boards to provide the various powering scheme – the main PCB is simply a carrier One plug-in per finger, coming in different flavours SPi plug-in, Pseudo SPi (with own shunt regulation and bypass circuitry) DC-DC powering Requirement for floating power supply I/P SPi will be(?) configurable using SCTDAQ Direct connection to hybrid VDD/VCC for auxiliary powering Allows for more thorough testing of ABCn powering Over/under voltage scenarios + direct current monitoring 9 Hybrid Powering and Readout Module Integration Working Group 17 th July 2008 Ashley Greenall

10 Shunt Regulator MMMM Linear Regulator Sensor Pseudo-SPi RX TX RX TX Power In VCC VDD Shunt Regulator Linear Regulator Power Out/In VCC VDD LV3 Power Out LVDS TX (Module Data) Powered from SCTDAQ LVDS RX (CLK,COM, etc.) Powered from Module VDD ABCn’s Operate in Legacy mode Data rate limited to 40MHz SCTDAQ Plug-in Circuit Hybrid connections made using wire-bonds Hybrid 0Hybrid 1 Hybrids are floating w.r.t. each other Auxiliary Power connections Floating Power Supply Powering and Readout Conceptually Module Integration Working Group 17 th July 2008 Plug-in Circuit SPi DC-DC

11 A Tentative Roadmap July’08 begin layout of hybrid Will be fabricated as a Cu Kapton flex circuit Using 35µm Cu (final version will use 12µm Cu) – build will otherwise be identical Removes any uncertainty regarding asic/hybrid operation Circuit will be laminated to rigid base board (FR4, carbon, ??) Expect hybrid circuit(s) to start to become available Oct’08 Circuits are being designed for both ASIC and Power evaluation ABCns due back Oct’08? First testing begins of asics Expect release of ABCn’s Nov/Dec’08? Module Integration Working Group 17 th July 2008 Consider using 18µm instead?

Proposal - continued Hybrids for staves are challenged by available area at ends Hybrid-2: for testing on stave –Assume MCC(s) is not available –Provide MCC function with either COTS chips or an FPGA, real-estate issue –Can consider a very wide hybrid (35 mm) to accommodate this, which still fits on stave –Aim for early 2009 Hybrid-3: on stave with MCC(s) –Push for minimum area –Impact on MCC aspect ratio

What it means – hybrid on sensor (unbridged) with integrated bus cable Critical dimensions Notes: Min. length of hybrid is 96.3mm <2mm real estate available at ends, assuming sizing is to 100mm sensor Where to locate MCC etc? (tape topology means 2 devices: 1 for power and 1 for digital I/O?) Consider reducing gap between ABCns doesn’t help. A reduction of 0.5mm/gap increases asic-to-sensor bonding angle to 35º (max is 18º) Necessary to increase hybrid length, will overhang sensor (rigidise?) Dimensions fixed – no other option! Ashley Greenall

40 MHz Beam Clock x2 x4 Data interleave takes 2 80 MHz streams into MHz stream ABCnext, 2 strings of 10 dataout dataclock multiplier U1 U2 Simplified hybrid scheme without a real MCC

Required Die U1: clock multiplier: candidate identified U2: data MUX: candidate identified 3 channels of LVDS receiver 1 channel of LVDS driver Serial powering components

Area Strongly advocate an aggressive minimum area design for Hybrid-3 –Goal would be 97+? mm x 20 mm –Consider running bus work under the chips, not just in the space between chips (asymmetric design) –Driven by ceramic hybrid experience –Impact on location of pads in ABCnext Ver2? 5mm

100 mm 20 mm A goal would be to fit all the required die, and on-hybrid buswork in the 5mm zone or (lines) under the chips Layer (from bottom up) 1)Static shield layer 2)Traces and power 3)Traces and ground 4)Component and bond pads Hybrid real estate

40 MHz Beam Clock x2 x4 Data mux takes 2 80 MHz streams into one 160 MHz stream ABCnext, 2 strings of 10 dataout dataclock multiplier com clk bco L1 mux Wiring scheme for minimum area hybrid, route below chips