16/06/20151 Wireless Network on a Chip Joseph Thomas Special Topics in SoC

16/06/20152 Introduction Wireless systems have excellent channeling capability and low-cost implementation. Size of antennas to be comparable with their wavelengths. As the CMOS device dimensions continue to scale down, operating speeds of CMOS devices will exceed 100 GHz in the near future. The optimal aperture size of the antenna is on the order of 1mm2, which is too large to be implemented.

16/06/20153 Time domain simulation of signal through (a) CPW(b) metal line Conventional metal lines with narrow geometry are inadequate Microwave txion in guided mediums, have low attunuation around 200GHz

16/06/20154 Wireless NoC(LAN) ULSI Chips Capacitive Couplers RF Circuits Off-chip,in- package CPW

16/06/20155 Top- Level Schematic of FDMA interconnect Multiple Access Techniques Modern FDMA and CDMA algorithms used to alleviate cross channel interference in the shared medium FDMA

16/06/20156 Block Diagram FDMA Transmitter FDMA Reciever Frequency bandsof I/O channels 5~20GHz in each channel to provide a data rate of 5~40Gb/s.

16/06/20157 CDMA Interconnect Operation of a CDMA- interconnect with two I/O subchannels CDMA

16/06/20158 Top level Schematic of a CDMA Interconnect

16/06/20159 Conclusion An implementation of Wireless Network on a Chip was discussed. Unlike traditional ”passive” metal interconnect, the ”active” wireless interconnect is based on capacitive coupling, low loss and dispersion free microwave signal transmission and modern multiple access algorithms.