technische universiteit eindhoven ‘Nothing is built on stone; all is built on sand, but we must build as if the sand were stone.’ Jorge Luis Borges (Argentine writer ) Department of Electrical Engineering Electronic Systems Modeling of Architectures Embedded Computer Architecture 5KK73 Henk Corporaal Bart Mesman Hamed Fatemi 2011

5kk73 Electronic Systems 2 Outline We will look at models for Area, Delay and Energy Processor structure Register files - Register cell Model (area, power, delay) details for several register file configurations Apply this to the Imagine architecture Stream register file (SRF) Network

5kk73 Electronic Systems 3 Processor Single processor Instruction Memory (IM) Controller Processing Element (PE) Register File (RF) ALU Data Memory (DM) SIMD Multiple PEs VLIW Multiple ALUs Multi-Processor Several processors Connected by a bus or network IM Controller RFALUDM Network PE

5kk73 Electronic Systems 4 Register File (RF) Area model Assume: p = number of ports For large RF row decoder small compared to cell area 1-Bit area = w*h (tracks) Schematic of 1 register cell 1 wordline and bitline per port needed If p is large 1-bit of size w*h

5kk73 Electronic Systems 5 Register file (RF) Delay model Delay (d): Wire Propagation delay Fan-in/out delay Delay ~ wire length ~ connected cells R = number of registers, each b bits wide => N bits = bR Assuming square bit-layout Note: for N FUs (ALUs), p ~ 3N, R ~ N → d ~ N 3/2 (for large p wiring dominates)

5kk73 Electronic Systems 6 Register file (RF) Power model Register file Power (P): Proportional to the capacitance that must be switched for each access In each access every bit-line and one word-line  bit-line capacitance Each port drives (bR) 1/2 bit lines Each bit line has length (h+p) (bR) 1/2 If p is large: power is dominated by wire capacitance Note: for N FUs (ALUs), p ~ 3N, R ~ N → P ~ N 3

5kk73 Electronic Systems 7 Register File organization Processor with one level register Central (shared register file) DRF (distributed register file): ALU 1 ALU N ALU 1ALU N

5kk73 Electronic Systems 8 Comparing Area model of Central and Distributed RF Central (shared) RF : 2 read ports, one write port per ALU R= rN: number of registers of b bits r: number of register per ALU N: number of ALUs DRF : Only 2 ports: one read, one write This would give A(1 RF) ~ N Area of switch has same area cost complexity Square layout & organization of the DRF, including 2N*N crossbar

5kk73 Electronic Systems 9 Delay and Power models of central versus distributed RF Assume N ALUs Central RF: #registers R=rN #ports p =3N Large N DRF: Constant #registers per ALU #ports p=2 (also constant!) DRF has a fixed delay and power (per RF) Wire propagation determines delay and power (for large N) For large N

5kk73 Electronic Systems 10 Register File Register (memory) storage and communication between ALUs are critical parts for area, energy and performance in media processor. Hierarchical register storage

5kk73 Electronic Systems 11 2-levels register files (Hierarchical) Central: RF1 serves the ALUs, while RF2 is used to cover the memory latency Overall tendency for Area is the same as having one level RF ALU 1 ALU N RF2 (level 2) RF1 (level 1) DRF: ALU 1ALU N RF2 (level 2) RF1 (level 1)

5kk73 Electronic Systems 12 Register Files Processor with stream register files: Replace each port into the memory staging RF with a stream buffer All stream buffers share a single port into the memory staging RF, allowing that single physical port to act as many logical ports. Central: ALU 1 ALU N

5kk73 Electronic Systems 13 Register Files DRF: The payoff the transformation into a stream architecture is that we can achieve an area proportional to N^2, since R2 (memory storage) only needs 1 port. We also have to add in the area of the stream buffers, which grows as N^2 with a very small constant. ALU 1ALU N

5kk73 Electronic Systems 14 Results area per ALU (Normalized to 1 ALU)

5kk73 Electronic Systems 15 Results Local delay

5kk73 Electronic Systems 16 Results Power overhead

5kk73 Electronic Systems 17 Imagine Architecture Die Photo of ImagineCell placement of Imagine

5kk73 Electronic Systems 18 Imagine Floorplan 22 million transistors 500 MHz Area, Energy, Delay models Clusters, Micro- controller, SRF, Network Interface

5kk73 Electronic Systems 19 Stream register File

5kk73 Electronic Systems 20 Network: Area of network grows with (like DRF switch) : More details in khailany paper [2003]

5kk73 Electronic Systems 21 Exploration Intra-cluster scaling

5kk73 Electronic Systems 22 Exploration Inter-cluster scaling

5kk73 Electronic Systems 23 end More details: Scott Rixner, William J. Dally, Brucek Khailany, Peter Mattson, Ujval J.Kapasi, and John D. Owens. Register Organization for Media Processing. In Proceedings of the 6th International Symposium on High-Performance Computer Architecture (HPCA), pages 375–386, Toulouse, France, January IEEE Computer Society. Brucek Khailany, William Dally, Scott Rixner, Ujval Kapasi, John Owens, and Brian Towles. Exploring the vlsi scalability of stream processors. In Proceedings of the Ninth Symposium on High Performance Computer Architecture (HPCA), pages 153– 164, Anaheim, California, USA, February IEEE Computer Society.