1 Lucas-Lehmer Primality Tester Presentation 6 March 1st 2006 Team: W-4 Nathan Stohs W4-1 Brian Johnson W4-2 Joe Hurley W4-3 Marques Johnson W4-4 Design Manager: Prateek Goenka Overall Objective: Modular Arithmetic unit with a creative use This is my presentation, there are others like it but this one is mine

2 Status Finished –Project Chosen –C simulations –Behavioral Verilog –Structural Verilog –Revised Floor Plan –Schematics ( 98%) In Progress –Top Level Simulations –Layout –Layout Simulations To Do –Continue Layout –Layout Simulations –Pathmill Simulation on Top Level

3 Design Decisions Optimization –Got rid of universal Shifter –Implemented Shifter_Left Shifter_Right –Stressed special cases over universal parts –Cut out 4,000 transistors

4 Transistor Counts (Old) ModuleTransistor Count FSM300 Mod Calc2440 Counter1656 Mod Multiply15302 Mod_Add Shifters Registers1848 Compare for zero92 Total21638

5 Transistor Counts (New) ModuleTransistor Count Count2,664 Mod_Multiply11,120 Mod_Add1282 Partial Products8,676 Counter266 Dff_re (16)896 Sub_16704 Compare36 Mod_P1,280 Top Level Flops896 FSM700 Total17,400

6 Power Consumption ModulePower Count53.81 uW Mod_Multiply? Mod_Add128.8 uW Partial Products368 uW Counter36.77 uW Dff_re (16)260 uW Compare149.2 pW Mod_P397.6 uW Top Level Flops39.6 uW FSM?

7 Shift_Left

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10 Shift_Right

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13 Mod_P

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16 Partial Product

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19 Pathmill Results Shift_Left =.610 ns Shift_Right =.610 ns Mod_P =.610 ns Mod_Add = ns Partial_Products = ns

20 Initial Layout

21 More Layout

22 Block Area Estimates (Old) ModuleArea (μm 2 ) FSM900 Mod Calc3500 Counter6000 Mod Multiply75000 Registers3000 Compare for zero300 Total88300

23 Block Area Estimates (Updated) ModuleArea (μm 2 ) Count13,200 Mod_Mult54,500 Sub_163,500 Compare200 Mod_P6,500 Top Level Flops4,400 FSM3,500

24 Updated Floorplan

25 What’s Next Continue Layout Pathmill Simulations for Top Level Simulate Layout

26 Questions?