Parking Pal Presentation #8 Team M1: Anna Kochalko Chris Moody Hong Tuck Liew John Wu Team TA: Kartik Murthy October 22, 2007 Gate Level Layout Your digital parking meter of the future!

Status Project Chosen Options explored and eliminated Wrote Java Implementation Specification defined Verilog obtained/modified Test Benches Schematic Design Basic Layout  Layout  Simulations

Metal Layer Usage In Components BCD (2 Metal layers – M1,M2) Encryption(4 Metal layers – M1,M2,M3,M4) – no over routing Multiplier(3 Metal layers- M1, M2, M3) Adder/ Subtractor (2 Metal layers – M1,M2) Comparator (2 Metal layers – M1, M2) SRAM (4 layers – M1, M2) Muxes (2 layers – M1, M2)

SRAM (Single Cell)

SRAM Waveform

SRAM (the bigger picture)

Full-Adder – 2-layer, 5.58 height

ExtractedRC Full Adder simulation

FLOORPLAN

Encryption Module

Completed modules AND, NAND, OR, NOR, XOR, XNOR (2,3,4 inputs) Full adder, half adder D_flip_flop t-gate 1bit mux

Power Gated VDD line  PMOS or powered gate? VDD lines implemented for all modules