1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities and architectural bodies behavioral, structural, and dataflow views examples

2 hardware description languages (HDL's): HDL is a language to describe hardware, just like it says; typically a HDL tries to use programming-language-type syntax and constructs to describe hardware, allowing the user to avoid the use of schematics

3 Some things HDL's must deal with: parallel activity (e.g., in a half adder, both the XOR and AND gates receive inputs simultaneously) vector inputs (e.g., in an 8-bit adder, the inputs are each 8 bits and the output is 9 bits) timing--both sequential and combinational logic (e.g., in a register the interaction between the clock input and the state changes must be described) levels of abstraction ideally will support both analysis and synthesis for hardware components/systems

4 intellectual property (IP): HDL's are an effective way to describe components in which the internal workings ("intellectual property") are proprietary but the interface to other components must be public "popular" HDL's: VHDL, Verilog Both have “AMS” (Analog and Mixed Signal) extensions

5 Two main HDLs: VHDL / Verilog VHDL--Very High Speed Integrated Circuit (VHSIC) Hardware Description Language Standards--IEEE ; ; Ada-like language Additions--VHDL-AMS--Analog & Mixed Signal Verilog—1985; proprietary to Cadence until 1990 (“open Verilog”) C-like language Additions—Verilog-AMS—Analog & Mixed Signal NOTE: this course is NOT designed to make you a VHDL or Verilog expert! The Altera tools (as well as other synthesis tools) work best with simpler HDL constructs (e.g., structural representations, modest levels of nesting)

6 VHDL and Verilog: Behavioral, Structural, and “Dataflow" views supported Physical views generally not supported --descriptions do not encompass the low-level physical details of a design --in particular descriptions can be "technology independent"; this supports REUSABILITY --for simulation, may add details of a particular technology [this quarter—HDL designs are tied to the specific technology of the chosen Altera device] Both languages allow for “testbenches” to aid simulaton (altera does not support the testbench concept; best- supported simulation is through graphical waveforms)

7 what can HDLs be used for? design entry simulation ("analysis"): simulators are examples of "discrete event simulators" E1 E11 E2 E12 E22 E3 E4 E111 E41 synthesis: HDL description can be turned into a circuit layout by powerful "silicon compilers" time

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9 VHDL *entity—interface to the outside world *architectural body—functionality *one entity can be paired with several architectural bodies, for example a structural body and a behavioral body

10 Note: keywords, comment, “entity” syntax

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14 Full adder example:

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25 Verilog: Much of the following is taken from the introduction by Dan Hyde at: Other references can be found at: Architectural, behavioral, gate, and switch levels supported Gate level: logic elements (structural) Switch level: transistor level Verilog program can be used for design, simulation, synthesis Basic construct: module Verilog program consists of interconnected modules Usually a “top” module encapsulates all the others NOTE: Altera does not allow simulation statements

26 fig_A1_01 Verilog: a C-like language Basic parts of a Verilog module:

27 Example: a simple structural module in Verilog

28 fig_A1_09 Another example of a structural module in Verilog:

29 Some simple examples of combinational logic: // NAND gate (behavioral model) module NAND(in1, in2, out); input in1, in2; output out; assign out = ~(in1 & in2); endmodule //AND gate (structural module) module AND(in1, in2, out); input in1, in2; output out; wire w1; NAND NAND1(in1, in2, w1); NAND NAND2(w1, w1, out); endmodule

30 fig_A1_02 Typical declarations (“vectors”):

31 fig_A1_03 Verilog computation and initialization examples: (myWires[2] is output, and gate is named a1)

32 fig_A1_07 Verilog combinational functions-structural primitives:

33 table_A1_00

34 table_A1_01

35 fig_A1_10 Modeling delays:

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41 Dataflow: continuous assignment Syntax: Assign destination = source *Destination cannot be a register or a function *any change in rhs forces a change in lhs—assignment is “always active” Examples:

42 fig_A1_16 (delays added) Inputs / outputs:

43 fig_A1_19 Rise and fall times can also be added

44 fig_A1_21 Dataflow models of sequential logic can be constructed:

45 Behavioral level: In C or C++, execution is sequential In Verilog execution is concurrent *Program is a collection of initial or always blocks; *Each block is a separate flow of control, independent of the others *Each block is defined by begin and end statements *Blocks cannot be nested Two types of procedural assignment: Blocking: sequential: A = B; Nonblocking: parallel: A <= B; Both can have delays added Example:

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47 fig_A1_24 Additional examples from text:

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52 fig_A1_29