The Concurrent Matching Switch Architecture Bill Lin (University of California, San Diego) Isaac Keslassy (Technion, Israel)

Slides:



Advertisements
Similar presentations
1 EE384Y: Packet Switch Architectures Part II Load-balanced Switch (Borrowed from Isaac Keslassys Defense Talk) Nick McKeown Professor of Electrical Engineering.
Advertisements

1 Maintaining Packet Order in Two-Stage Switches Isaac Keslassy, Nick McKeown Stanford University.
Fast Buffer Memory with Deterministic Packet Departures Mayank Kabra, Siddhartha Saha, Bill Lin University of California, San Diego.
Optimal-Complexity Optical Router Hadas Kogan, Isaac Keslassy Technion (Israel)
Modeling the Interactions of Congestion Control and Switch Scheduling Alex Shpiner Joint work with Isaac Keslassy Faculty of Electrical Engineering Faculty.
High-Performance Networking Group Isaac Keslassy, Nick McKeown
Submitters: Erez Rokah Erez Goldshide Supervisor: Yossi Kanizo.
Nick McKeown CS244 Lecture 6 Packet Switches. What you said The very premise of the paper was a bit of an eye- opener for me, for previously I had never.
Frame-Aggregated Concurrent Matching Switch Bill Lin (University of California, San Diego) Isaac Keslassy (Technion, Israel)
A Load-Balanced Switch with an Arbitrary Number of Linecards Isaac Keslassy, Shang-Tse Chuang, Nick McKeown.
Routers with a Single Stage of Buffering Sundar Iyer, Rui Zhang, Nick McKeown High Performance Networking Group, Stanford University,
Scaling Internet Routers Using Optics UW, October 16 th, 2003 Nick McKeown Joint work with research groups of: David Miller, Mark Horowitz, Olav Solgaard.
Towards Simple, High-performance Input-Queued Switch Schedulers Devavrat Shah Stanford University Berkeley, Dec 5 Joint work with Paolo Giaccone and Balaji.
Isaac Keslassy, Shang-Tse (Da) Chuang, Nick McKeown Stanford University The Load-Balanced Router.
A Scalable Switch for Service Guarantees Bill Lin (University of California, San Diego) Isaac Keslassy (Technion, Israel)
Making Parallel Packet Switches Practical Sundar Iyer, Nick McKeown Departments of Electrical Engineering & Computer Science,
1 Input Queued Switches: Cell Switching vs. Packet Switching Abtin Keshavarzian Joint work with Yashar Ganjali, Devavrat Shah Stanford University.
Packet-Mode Emulation of Output-Queued Switches David Hay, CS, Technion Joint work with Hagit Attiya (CS, Technion), Isaac Keslassy (EE, Technion)
1 Comnet 2006 Communication Networks Recitation 5 Input Queuing Scheduling & Combined Switches.
Scaling Internet Routers Using Optics Producing a 100TB/s Router Ashley Green and Brad Rosen February 16, 2004.
1 Architectural Results in the Optical Router Project Da Chuang, Isaac Keslassy, Nick McKeown High Performance Networking Group
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Input-Queued.
Using Load-Balancing To Build High-Performance Routers Isaac Keslassy, Shang-Tse (Da) Chuang, Nick McKeown Stanford University.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion MSM.
CSIT560 by M. Hamdi 1 Course Exam: Review April 18/19 (in-Class)
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion The.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Scaling.
A Load-Balanced Switch with an Arbitrary Number of Linecards Isaac Keslassy, Shang-Tse (Da) Chuang, Nick McKeown Stanford University.
Scaling Internet Routers Using Optics Isaac Keslassy, Shang-Tse Da Chuang, Kyoungsik Yu, David Miller, Mark Horowitz, Olav Solgaard, Nick McKeown Department.
The Crosspoint Queued Switch Yossi Kanizo (Technion, Israel) Joint work with Isaac Keslassy (Technion, Israel) and David Hay (Politecnico di Torino, Italy)
1 Internet Routers Stochastics Network Seminar February 22 nd 2002 Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University.
1 EE384Y: Packet Switch Architectures Part II Load-balanced Switches Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University.
A combinational media access protocol for multicast traffic in single-hop WDM lans Student : T.H Lin Teacher : H.T Wu Date : 7.28.
1 Trend in the design and analysis of Internet Routers University of Pennsylvania March 17 th 2003 Nick McKeown Professor of Electrical Engineering and.
COMP680E by M. Hamdi 1 Course Exam: Review April 17 (in-Class)
1 Achieving 100% throughput Where we are in the course… 1. Switch model 2. Uniform traffic  Technique: Uniform schedule (easy) 3. Non-uniform traffic,
Optimal Load-Balancing Isaac Keslassy (Technion, Israel), Cheng-Shang Chang (National Tsing Hua University, Taiwan), Nick McKeown (Stanford University,
1 Netcomm 2005 Communication Networks Recitation 5.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Maximal.
August 20 th, A 2.5Tb/s LCS Switch Core Nick McKeown Costas Calamvokis Shang-tse Chuang Accelerating The Broadband Revolution P M C - S I E R R.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Scheduling.
Distributed Scheduling Algorithms for Switching Systems Shunyuan Ye, Yanming Shen, Shivendra Panwar
1 Growth in Router Capacity IPAM, Lake Arrowhead October 2003 Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University.
Pipelined Two Step Iterative Matching Algorithms for CIOQ Crossbar Switches Deng Pan and Yuanyuan Yang State University of New York, Stony Brook.
Localized Asynchronous Packet Scheduling for Buffered Crossbar Switches Deng Pan and Yuanyuan Yang State University of New York Stony Brook.
1 IP routers with memory that runs slower than the line rate Nick McKeown Assistant Professor of Electrical Engineering and Computer Science, Stanford.
Load Balanced Birkhoff-von Neumann Switches
Nick McKeown CS244 Lecture 7 Valiant Load Balancing.
Merits of a Load-Balanced AAPN 1.Packets within a flow are transported to their correct destinations in sequence. This is due to the 1:1 logical connection.
Belgrade University Aleksandra Smiljanić: High-Capacity Switching Switches with Input Buffers (Cisco)
FiWi Integrated Fiber-Wireless Access Networks
High Speed Stable Packet Switches Shivendra S. Panwar Joint work with: Yihan Li, Yanming Shen and H. Jonathan Chao New York State Center for Advanced Technology.
Summary of switching theory Balaji Prabhakar Stanford University.
Advance Computer Networking L-8 Routers Acknowledgments: Lecture slides are from the graduate level Computer Networks course thought by Srinivasan Seshan.
Designing Packet Buffers for Internet Routers Friday, October 23, 2015 Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford.
A.SATHEESH Department of Software Engineering Periyar Maniammai University Tamil Nadu.
Applied research laboratory 1 Scaling Internet Routers Using Optics Isaac Keslassy, et al. Proceedings of SIGCOMM Slides:
ISLIP Switch Scheduler Ali Mohammad Zareh Bidoki April 2002.
1 Performance Guarantees for Internet Routers ISL Affiliates Meeting April 4 th 2002 Nick McKeown Professor of Electrical Engineering and Computer Science,
Stress Resistant Scheduling Algorithms for CIOQ Switches Prashanth Pappu Applied Research Laboratory Washington University in St Louis “Stress Resistant.
Belgrade University Aleksandra Smiljanić: High-Capacity Switching Switches with Input Buffers (Cisco)
Buffered Crossbars With Performance Guarantees Shang-Tse (Da) Chuang Cisco Systems EE384Y Thursday, April 27, 2006.
SNRC Meeting June 7 th, Crossbar Switch Scheduling Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University
1 How scalable is the capacity of (electronic) IP routers? Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University
Throughput of Internally Buffered Crossbar Switch Saturday, February 20, 2016 Mingjie Lin
Block-Based Packet Buffer with Deterministic Packet Departures Hao Wang and Bill Lin University of California, San Diego HSPR 2010, Dallas.
A Load Balanced Switch with an Arbitrary Number of Linecards I.Keslassy, S.T.Chuang, N.McKeown ( CSL, Stanford University ) Some slides adapted from authors.
A Load-Balanced Switch with an Arbitrary Number of Linecards Offense Anwis Das.
CS 740: Advance Computer Networks Hand-out on Router Design
Advance Computer Networking
Presentation transcript:

The Concurrent Matching Switch Architecture Bill Lin (University of California, San Diego) Isaac Keslassy (Technion, Israel)

IEEE INFOCOM, Barcelona, April 23-29, Motivation  Traffic demands expected to grow, driven in part by increasing broadband adoption  10x increase in broadband subscription in just last 3 years, already over 100 million subscribers  Gbps fiber to homes emerging (GPON, GEPON, EPON, BPON …)  Larger routers needed for consolidation  Operators need scalable routers that provide good performance

IEEE INFOCOM, Barcelona, April 23-29, Limitations of Previous Routers  Output-Queueing (OQ) Switch  Well-known to provide good performance, but scalability hampered by need for internal N speedup  Crossbar Switches, using Input-Queueing (IQ) or Combined Input-Output Queueing (CIOQ)  Huge body of literature, but scalability hampered by need for centralized scheduling and arbitrary per- packet switch configurations

IEEE INFOCOM, Barcelona, April 23-29, Limitations of Previous Routers  Load-Balanced Routers  No centralized scheduler  Scalable fixed configuration switch fabric in optics  Guarantees 100% throughput  100 Tb/s design with 160 Gb/s linecards shown  But packets may be delivered “out-of-order”

IEEE INFOCOM, Barcelona, April 23-29, Out R R R R/N R R R Basic Load-Balanced Router R/N In Linecards A1 A2 A3 B1 C1 C2 B1 B2 C1

IEEE INFOCOM, Barcelona, April 23-29, Out R R R R/N R R R Basic Load-Balanced Router R/N In Linecards A1 A2 A3 B1 C1 C2 B1 B2 C1 Many Fabric Options (any spreading device)  Space: Full uniform mesh  Wavelength: Static WDM  Time: Round-robin switches Just need fixed uniform rate channels at R/N No dynamic switch reconfigurations Many Fabric Options (any spreading device)  Space: Full uniform mesh  Wavelength: Static WDM  Time: Round-robin switches Just need fixed uniform rate channels at R/N No dynamic switch reconfigurations

IEEE INFOCOM, Barcelona, April 23-29, Out R R R R/N R R R Basic Load-Balanced Router R/N In Linecards A1 A2 A3 B1 C1 C2 B1 B2 C1 Out of Order !

IEEE INFOCOM, Barcelona, April 23-29, Packet Ordering Problem  Out-of-order packet delivery is undesirable (e.g. bad for TCP)  Previous techniques (e.g. EDF, UFS, FOFF)  Accumulate and delay packets at input/middle ports  And/or delay and re-order packets at middle/output ports  However, these techniques are unsatisfactory because they add substantial delays

IEEE INFOCOM, Barcelona, April 23-29, Impact on Avg. Delay (N = 128, uniform traffic) Basic Load-Balanced UFS FOFF Significant Delay

IEEE INFOCOM, Barcelona, April 23-29, Concurrent Matching Switch (CMS)  Basic idea  Retain load-balanced router structure and scalability of a fixed optical mesh, no dynamic reconfiguration  Instead of packets, load-balance “request tokens” to N parallel “schedulers”  Each scheduler independently solves its own matching  Packets delivered in order based on matching results Goal is to provide much lower average delay than accumulation-based methods for ensuring packet order while retaining 100% throughput and scalability

IEEE INFOCOM, Barcelona, April 23-29, Out R R R R R R Architecture Linecards A1 B1 C1 C2 C1 B2 C2 Retain Fixed Configuration Meshes BUT move packet buffers to INPUT A2 A3 A4

IEEE INFOCOM, Barcelona, April 23-29, Out R R R R R R Architecture Linecards A1 B1 C1 C2 C1 B2 C2 A2 A3 A Add N 2 Token Counters

IEEE INFOCOM, Barcelona, April 23-29, Out R R R R R R Arrival Phase Linecards A1 C1 C2 C1 C2 A2 A3 A B1 B2 A1 A2 B1 B2 C2 C3 C4

IEEE INFOCOM, Barcelona, April 23-29, Out R R R R R R Arrival Phase Linecards A1 C1 C2 C1 C2 A2 A3 A B1 B2 B1 B2 C2 C3 C4 A1 A2

IEEE INFOCOM, Barcelona, April 23-29, Out R R R R R R Arrival Phase Linecards A1 C1 C2 C1 C2 A2 A3 A B1 B2 A1 A2 B1 B2 C2 C3 C4

IEEE INFOCOM, Barcelona, April 23-29, Out R R R R R R Arrival Phase Linecards A1 C1 C2 C1 C2 A2 A3 A B1 B2 A1 A2 B1 B2 C2 C3 C4

IEEE INFOCOM, Barcelona, April 23-29, Out R R R R R R Matching Phase Linecards A1 C1 C2 A2 A3 A B1 B2 A1 A2 B1 B2 C1 C2 C1 C2 C3 C4

IEEE INFOCOM, Barcelona, April 23-29, Out R R R R R R Matching Phase Linecards A1 C1 C B1 A2 A3 A4 B1 A1 A2 C1 B1 B2 C2 C1 C2 C3 C4

IEEE INFOCOM, Barcelona, April 23-29, Out R R R R R R Matching Phase Linecards A1 C1 C B1 A2 A3 A4 B1 B2 C3 C4 A1 A2 C1 B1 C1 B2 C2

IEEE INFOCOM, Barcelona, April 23-29, Out R R R R R R Departure Phase Linecards A1 C1 C B1 A2 A3 A4 B1 B2 C3 C4 A1 A2 C1 B1 C1 B2 C2

IEEE INFOCOM, Barcelona, April 23-29, Distributed Operation  All linecards operate in parallel in a fully distributed manner  Arrival, matching, and departure phases overlap in a pipeline manner

IEEE INFOCOM, Barcelona, April 23-29, Main Ideas  Each middle linecard acts as a “micro-router” with 1/N th of the arrival traffic  Therefore, it gets N time slots to think about the schedule, time complexity amortized by a factor of N  If each micro-router can guarantee 100% throughput, so can the overall switch  Each micro-router can work the way that it wants, leveraging huge body of existing work on scheduling CMS provides a new way of aggregating routers together. Therefore, provides a new way of thinking about scaling routers.

IEEE INFOCOM, Barcelona, April 23-29, Practicality  Well-studied randomized approximations to Maximum Weighted Matching have been shown to achieve very good results [Tassiulas 1998] [Giaccone, Prabhakar & Shah, 2003]  These algorithms only require O(N) complexity using sequential hardware, but can provide 100% throughput guarantees with no speedup and good delay results  Amortized over N time slots, CMS with these scheduling algorithms can achieve  O(1) time complexity (independent of switch size)  100% throughput  Good delay results  Packet ordering

IEEE INFOCOM, Barcelona, April 23-29, Experimental Results (N = 128, uniform traffic) Basic Load-Balanced UFS FOFF CMS Difference of N time slots for matching phase

IEEE INFOCOM, Barcelona, April 23-29, Conclusions  CMS is scalable  Leverages scalability of fixed optical meshes  Fully distributed  Can achieve O(1) time complexity  CMS achieves good performance  Guarantees 100% throughput  Guarantees packet ordering  Experimentally achieves low packet delays  CMS provides new way of thinking about scaling routers and connects huge body of existing literature on scheduling to load-balanced routers

Thank You