Low Power Implementation of Scan Flip-Flops Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn, AL

Objectives Scan flip-flop overview Ways to incorporate low power design Benchmark circuit Results

Scan Flip-Flop Combinational logic Scan flip- flops Primary inputs Primary outputs Scan-in SI Scan-out SO Scan enable SE DFF mux SE SI D D D’ SO 0101

How does is work? Combinational logic FF=0 FF=1 Primary inputs Primary outputs Scan-in 010 Scan-out 100

Low Power Scan Flip-Flop Scan FF cell DFF mux SE SI D SO D’ DFF mux SE SI D D’ SO 0101 Low power scan FF cell

Validation of lpsff Q grounds upon entering scan-mode QS provides output to scan chain

Benchmark Circuit S5378 –35 Inputs –49 Outputs Standard –179 D-type flip-flops –1775 Inverters –239 Or gates –765 Nor gates Flattened/optimized –Scan FF 967 complex gates –Low-Power Scan FF 1152 complex gates

Test Patterns Combinational logic FF Primary inputs Primary outputs Scan-in Always Random Scan-out Primary Input Patterns 55 h AA h All 1s All 0s Random but constant 1 Random but constant 2 All Random

Gate Transitions AAh All 0 55h All 1 Rand 2 Rand 1 All Rand

Gate Events AAh All 0 55h All 1 Rand 2 Rand 1 All Rand

Average Power Consumption (uW) AAh All 0 55h All 1 Rand 2 Rand 1 All Rand

Power Reduction 55 h 35.1% AA h 22.8% All % All % Random 1 (const) 23.9% Random 2 (const) 18.8% All Random * 0% * sff  lpsff * Only encountered if entering into scan mode and the system didn’t know to latch the input signals.

Conclusion Low Power Scan Chain can result in up to 35% power reduction. Minimal 19% area overhead from standard scan chain flip-flop Average power reduction of 20-30% if input signals are held static

References TSMC 0.25um process parameters Mentor Graphics Leonardo for design synthesis Auburn’s PowerSim3 used for power measurements – Created by : Jins Alexander