Viterbi Decoder: Presentation #11 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 11: 12 th April 2004 Short Final Presentation Design Manager: Yaping Zhan Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun

Status , Integrated Circuits Design Project Design Proposal: (Done) Architecture Proposal: (Done) Gate level Design: (Done) Component Layout: (Done) Component Simulation: (Done) Chip Layout: (Done) Spice simulation of entire chip (In progress)

Marketing , Integrated Circuits Design Project  What is a Viterbi Decoder? Uses and applications Example  Why our design is useful? High speed Compact ~ 3 Slides

Algorithm Description , Integrated Circuits Design Project  Brief overview How/Why it works  Dataflow of our design Break down of each component ~ 5 Slides

Implementation , Integrated Circuits Design Project  Overview Decision on design goal – high speed  Schematic Description ~ 2 Slides

Verification , Integrated Circuits Design Project  Matlab Simulations Overview How/Why it works  Verilog Simulations Overview How/Why it works Behavioral/Structural  Top level schematic Simulation Overview How/Why it works  Top level layout Simulation LVS Spice ~ 15 Slides

Floorplan Evolution , Integrated Circuits Design Project  Floorplan ideas Overview Various implementations  Initial floorplan Description Rejection  Final floorplan Description Acceptance ~ 8 Slides

Issues , Integrated Circuits Design Project  Floorplanning  Wiring Wrong connections Decisions on top level routing  Simulation Checking for critical path  Space Gripe ~ 1 Slide

Specifications , Integrated Circuits Design Project  Pin Specs  Part Specs Evolution (Intial, changes, final)  Chip Specs Evolution ~ 3 Slides

Layout , Integrated Circuits Design Project  Masks Active Poly Metals 1, 2, 3, 4  Full chip layout With overlaid floorplan ~ 8 Slides

Conclusions , Integrated Circuits Design Project ~ 1 Slide

Emulations , Integrated Circuits Design Project  Matlab  Verilog  Schematic  LVS  Spice ~ 5 Slides

Allocation of slides , Integrated Circuits Design Project  Marketing  Algorithm Description  Implementation  Verification  Floorplan Evolution  Issues  Specifications  Layout  Conclusions  Emulations Total no. of slides ~ 50 Lingyan Saim Prateek Omar

Updates , Integrated Circuits Design Project  We were running full chip simulation but… Takes a long time People are very very very bad  Added counter Provides robustness to design Extra part

Added Counter

Final Dimensions , Integrated Circuits Design Project Total Area: um x um = 71, sq. um Transistor Count: 17, = 18,075 Transistor Density: Aspect Ratio: Estimated Clock Speed: 300 MHz. Clock Speed Achieved: 500 MHz.

18-525, Integrated Circuits Design Project Questions/Comments