Digital Integrated Circuits© Prentice Hall 1995 Memory SEMICONDUCTOR MEMORIES
Digital Integrated Circuits© Prentice Hall 1995 Memory Chapter Overview
Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Classification
Digital Integrated Circuits© Prentice Hall 1995 Memory Memory Architecture: Decoders
Digital Integrated Circuits© Prentice Hall 1995 Memory Array-Structured Memory Architecture
Digital Integrated Circuits© Prentice Hall 1995 Memory Hierarchical Memory Architecture
Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NOR ROM Layout
Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NOR ROM Layout
Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NAND ROM
Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NAND ROM Layout
Digital Integrated Circuits© Prentice Hall 1995 Memory Precharged MOS NOR ROM
Digital Integrated Circuits© Prentice Hall 1995 Memory Characteristics of State-of-the-art NVM
Digital Integrated Circuits© Prentice Hall 1995 Memory Read-Write Memories (RAM)
Digital Integrated Circuits© Prentice Hall 1995 Memory 6-transistor CMOS SRAM Cell
Digital Integrated Circuits© Prentice Hall 1995 Memory CMOS SRAM Analysis (Write)
Digital Integrated Circuits© Prentice Hall 1995 Memory CMOS SRAM Analysis (Read)
Digital Integrated Circuits© Prentice Hall 1995 Memory 6T-SRAM — Layout V DD GND Q Q WL BL M1 M3 M4M2 M5M6
Digital Integrated Circuits© Prentice Hall 1995 Memory Resistance-load SRAM Cell
Digital Integrated Circuits© Prentice Hall 1995 Memory 3-Transistor DRAM Cell
Digital Integrated Circuits© Prentice Hall 1995 Memory 3T-DRAM — Layout BL2BL1GND RWL WWL M3 M2 M1
Digital Integrated Circuits© Prentice Hall 1995 Memory 1-Transistor DRAM Cell
Digital Integrated Circuits© Prentice Hall 1995 Memory DRAM Cell Observations
Digital Integrated Circuits© Prentice Hall 1995 Memory 1-T DRAM Cell
Digital Integrated Circuits© Prentice Hall 1995 Memory Periphery
Digital Integrated Circuits© Prentice Hall 1995 Memory Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder
Digital Integrated Circuits© Prentice Hall 1995 Memory Dynamic Decoders
Digital Integrated Circuits© Prentice Hall 1995 Memory A NAND decoder using 2-input pre- decoders
Digital Integrated Circuits© Prentice Hall 1995 Memory 4 input pass-transistor based column decoder
Digital Integrated Circuits© Prentice Hall 1995 Memory 4-to-1 tree based column decoder
Digital Integrated Circuits© Prentice Hall 1995 Memory Sense Amplifiers
Digital Integrated Circuits© Prentice Hall 1995 Memory Differential Sensing - SRAM
Digital Integrated Circuits© Prentice Hall 1995 Memory Latch-Based Sense Amplifier
Digital Integrated Circuits© Prentice Hall 1995 Memory Open bitline architecture
Digital Integrated Circuits© Prentice Hall 1995 Memory DRAM Read Process with Dummy Cell
Digital Integrated Circuits© Prentice Hall 1995 Memory Programmable Logic Array
Digital Integrated Circuits© Prentice Hall 1995 Memory Pseudo-Static PLA
Digital Integrated Circuits© Prentice Hall 1995 Memory Dynamic PLA
Digital Integrated Circuits© Prentice Hall 1995 Memory Clock Signal Generation for self-timed dynamic PLA
Digital Integrated Circuits© Prentice Hall 1995 Memory PLA Layout
Digital Integrated Circuits© Prentice Hall 1995 Memory PLA versus ROM
Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Trends Memory Size as a function of time: x 4 every three years
Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Trends Increasing die size factor 1.5 per generation Combined with reducing cell size factor 2.6 per generation
Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Trends Technology feature size for different SRAM generations