EE296 Working with FPGA’s. (Field Programmable gate array) Team name: Altezza Team members: Richard Phomsouvanh (FPGA expert) Jason Leong (VHDL expert)

Slides:

Advertisements

Similar presentations

FPGA (Field Programmable Gate Array)

Advertisements

Comparison of Altera NIOS II Processor with Analog Device’s TigerSHARC

Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering.

VHDL - I 1 Digital Systems. 2 «The designer’s guide to VHDL» Peter J. Andersen Morgan Kaufman Publisher Bring laptop with installed Xilinx.

IN2305-II Embedded Programming Lecture 2: Digital Logic.

Chapter 10 Flip-Flops and Registers Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz.

Maciej Gołaszewski Tutor: Tadeusz Sondej, PhD Design and implementation of softcore dual processor system on single chip FPGA Design and implementation.

University Of Vaasa Telecommunications Engineering Automation Seminar Signal Generator By Tibebu Sime 13 th December 2011.

EELE 367 – Logic Design Module 2 – Modern Digital Design Flow Agenda 1.History of Digital Design Approach 2.HDLs 3.Design Abstraction 4.Modern Design Steps.

Week 1- Fall 2009 Dr. Kimberly E. Newman University of Colorado.

Stop Watch Sean Hicks Dongpu Jin ELEC 307 Project 2 Instructor: Alvaro Pinto April/12/2011.

Term Project Overview Yong Wang. Introduction Goal –familiarize with the design and implementation of a simple pipelined RISC processor What to do –Build.

Configurable System-on-Chip: Xilinx EDK

LabVIEW Design of Digital Integrated Circuits FPGA IC Implantation.

EE296 Working with the FPGA’s. (Field Programmable gate array) Team name: Altezza Team members: Richard Phomsouvanh (FPGA expert) Jason Leong (VHDL expert)

ECE Department: University of Massachusetts, Amherst Lab 1: Introduction to NIOS II Hardware Development.

Altera DE2 Board and Quartus II Software ECE 3450 M. A. Jupina, VU, 2014.

CSCE 430/830 A Tutorial of Project Tools By Dongyuan Zhan Feb. 4, 2010.

1 Chapter 7 Design Implementation. 2 Overview 3 Main Steps of an FPGA Design ’ s Implementation Design architecture Defining the structure, interface.

Programmable Array Logic (PAL) Fixed OR array programmable AND array Fixed OR array programmable AND array Easy to program Easy to program Poor flexibility.

Figure 1.1 The Altera UP 3 FPGA Development board

ALTERA UP2 Tutorial 1: The 15 Minute Design. Figure 1.1 The Altera UP 1 CPLD development board. ALTERA UP2 Tutorial 1: The 15 Minute Design.

Guest Lecture by Ben Magstadt CprE 281: Digital Logic.

CSE430/830 Course Project Tutorial Instructor: Dr. Hong Jiang TA: Dongyuan Zhan Project Duration: 01/26/11 – 04/29/11.

Cumulative Design Review: Interactive Teaching Device April 8 th, 2005 Lance Haney Micah Nance Nathan Young.

Chapter 4 Programmable Logic Devices: CPLDs with VHDL Design Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights.

EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab Spring 2009.

Guest Lecture by Ben Magstadt CprE 281: Digital Logic.

Computer Science, Software Engineering & Robotics Workshop, FGCU, April 27-28, 2012 FPGA: Field Programmable Gate Arrays Vincent Giannone Mentor: Dr. Janusz.

© 2011 Altera Corporation—Public Introducing Qsys – Next Generation System Integration Platform AP Tech Roadshow.

Lecture #3 Page 1 ECE 4110– Sequential Logic Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.No Class Monday, Labor Day Holiday 2.HW#2 assigned.

1 3-General Purpose Processors: Altera Nios II 2 Altera Nios II processor A 32-bit soft core processor from Altera Comes in three cores: Fast, Standard,

Status Report Atsushi Nukariya. FPGA training course ・ I solved 15 problems which are proposed by Uchida-san. ・ I used above circuit board. FPGA.

System Arch 2008 (Fire Tom Wada) /10/9 Field Programmable Gate Array.

Lecture #3 Page 1 ECE 4110– Sequential Logic Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.No Class Monday, Labor Day Holiday 2.HW#2 assigned.

© 2005 Altera Corporation SOPC Builder: a Design Tool for Rapid System Prototyping on FPGAs Kerry Veenstra Workshop on Architecture Research using FPGA.

EL 3101 EL310 Hardware Description Languages Spring 2015 Instructor: Ilker Hamzaoglu Teaching Assistant: Ercan Kalalı Web Site:

Introduction Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL) A hardware description language is a language or means used to describe or model a digital.

Flip-Flops and Registers

Galen SasakiEE 260 University of Hawaii1 Electronic Design Automation (EDA) EE 260 University of Hawaii.

Array Synthesis in SystemC Hardware Compilation Authors: J. Ditmar and S. McKeever Oxford University Computing Laboratory, UK Conference: Field Programmable.

ASIC 121: Practical VHDL Digital Design for FPGAs Tutorial 1 September 27, 2006.

Chapter 4 Programmable Logic Devices: CPLDs with VHDL Design Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights.

Lecture #3 Page 1 ECE 4110–5110 Digital System Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.HW#2 assigned Due.

Introducing the Nexys 2 Board CS 332 – Operating Systems 12/04/2011 by Otto Castell-R.

Anurag Dwivedi. Basic Block - Gates Gates -> Flip Flops.

EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

Lopamudra Kundu Reg. No. : of Roll No.:- 91/RPE/ Koushik Basak

 Seattle Pacific University EE Logic System DesignAlteraBoard-2 Altera Cyclone II (484 Pin BGA) 22 Pins.

COE4OI5 Engineering Design Chapter 1: The 15 minutes design.

Introduction to Field Programmable Gate Arrays Lecture 1/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May – 9 June 2007 Javier.

Performed by:Elkin Aleksey and Savi Esacov Instructor: Idan Shmuel המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי.

Teaching Digital Logic courses with Altera Technology

Embedded Systems Design with Qsys and Altera Monitor Program

CprE 281: Verilog Tutorial Ben Magstadt – Master’s Student Electrical Engineering.

VHDL From Ch. 5 Hardware Description Languages. History 1980’s Schematics 1990’s Hardware Description Languages –Increased due to the use of Programming.

A Brief Introduction to FPGAs

B0110 Fabric and Trust ENGR xD52 Eric VanWyk Fall 2013.

Introduction to the FPGA and Labs

EE296 Working with the FPGA’s. (Field Programmable gate array)

Figure 1.1 The Altera UP 1 CPLD development board.

EEE2135 Digital Logic Design Chapter 1. Introduction

Programmable Logic Devices: CPLDs and FPGAs with VHDL Design

Field Programmable Gate Array

Field Programmable Gate Array

Field Programmable Gate Array

Getting Started with Programmable Logic

(Lecture by Hasan Hassan)

Presentation transcript:

EE296 Working with FPGA’s. (Field Programmable gate array) Team name: Altezza Team members: Richard Phomsouvanh (FPGA expert) Jason Leong (VHDL expert) Jason Leong (VHDL expert)

Overview of the Project Get familiar with FPGA’s What is a FPGA? Implement I 2 C protocol using the FPGA What is the I 2 C Protocol? Further experiment with the capabilities of the FPGA.

What is a FPGA? F ield P rogrammable G ate A rray F ield P rogrammable G ate A rray Device containing programmable logic components and programmable interconnects. Device containing programmable logic components and programmable interconnects. FPGA is similar to a Programmable Logic Device. FPGA is similar to a Programmable Logic Device.

Logic Devices Thousands of logic devices Thousands of logic devices AND gates AND gates OR gates OR gates Flip Flops Flip Flops Mux Mux Decoders Decoders

Software Quartus II Web Edition CAD system Quartus II Web Edition CAD system VHDL VHDL Verilog HDL Verilog HDL Altera Hardware Description Language Altera Hardware Description Language Nios II Embedded Processor Nios II Embedded Processor C and C++ Programming C and C++ Programming

Plans for the Board EE260 Display EE260 Display LEDs, Toggle switches, Push-buttons, and 7-seg. LEDs, Toggle switches, Push-buttons, and 7-seg. Teaching Aid Teaching Aid Another way to test out logic designs Another way to test out logic designs See visual outputs See visual outputs Less error Less error In labs In labs

Overview of the Project Get familiar with FPGA’s What is a FPGA? Implement I 2 C protocol using the FPGA What is the I 2 C Protocol? Further experiment with the capabilities of the FPGA.

Complete I 2 C

Master module Master Controller AU DU Count Master SSU Master BIU

Module Components I 2 C VHDL Master/slave controllers Address Unit Data Unit Count unit

More Module Components Unfinished Master/Slave BIU Master SSU Slave SSU

Still not done Still need to perfect working with the FPGA Still need to perfect working with the FPGA Having all sorts of problems Having all sorts of problems Finish up the rest of VHDL files Finish up the rest of VHDL files Synthesize I 2 C on FPGA Synthesize I 2 C on FPGA Try get the LCD display to work. Try get the LCD display to work.

Ala gantt chart 3/152/11/282/153/13/294/125/7 Tasks Task circuit files AU/DU/Count Convert CCT to VHDL Task Tutorials Clock Task Master/Slave Controllers AU/DU/Count Top Layer Two boards talk LCD ???

Questions?