December 1, 2005 ELEC 6970 - Project Presentation 1 Dual-Voltage Supply for Power Reduction ELEC 6970 – Low Power Design Project Presentation by Muthubalaji.

Slides:

Advertisements

Similar presentations

Semiconductor Memory Design. Organization of Memory Systems Driven only from outside Data flow in and out A cell is accessed for reading by selecting.

Advertisements

9/15/05ELEC / Lecture 71 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

1 8-Bit Barrel Shifter Cyrus Thomas Ekemini Essien Kuang-Wai (Kenneth) Tseng Advisor: Dr. David Parent December 8, 2004.

Power Reduction Techniques For Microprocessor Systems

Leakage and Dynamic Glitch Power Minimization Using MIP for V th Assignment and Path Balancing Yuanlin Lu and Vishwani D. Agrawal Auburn University ECE.

Praveen Venkataramani Suraj Sindia Vishwani D. Agrawal FINDING BEST VOLTAGE AND FREQUENCY TO SHORTEN POWER CONSTRAINED TEST TIME 4/29/ ST IEEE VLSI.

Introduction to CMOS VLSI Design Lecture 13: SRAM

Introduction to CMOS VLSI Design Lecture 18: Design for Low Power David Harris Harvey Mudd College Spring 2004.

Multiobjective VLSI Cell Placement Using Distributed Simulated Evolution Algorithm Sadiq M. Sait, Mustafa I. Ali, Ali Zaidi.

Dec. 1, 2005ELEC Class Presentation1 Impact of Pass-Transistor Logic (PTL) on Power, Delay and Area Kalyana R Kantipudi ECE Department Auburn.

S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 14: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

August 12, 2005Uppalapati et al.: VDAT'051 Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells 9th VLSI Design & Test Symposium.

11/03/05ELEC / Lecture 181 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

9/08/05ELEC / Lecture 51 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Nov. 29, 2005 ELEC Class Presentation 1 Logic Redesign for Low Power ELEC 6970 Project Presentation By Nitin Yogi.

Introduction to CMOS VLSI Design SRAM/DRAM

Dec. 6, 2005ELEC Glitch Power1 Low power design: Insert delays to eliminate glitches Yijing Chen Dec.6, 2005 Auburn university.

Dec. 6, 2005ELEC Class Presentation1 Reducing Switching Capacitance Using Buffers Brad Hill.

Decomposition of Instruction Decoder for Low Power Design TingTing Hwang Department of Computer Science Tsing Hua University.

Nov. 29, 2005 ELEC Class Presentation 1 Reducing Voltage Supply Jins Davis Alexander.

Spring 07, Feb 27 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Power Consumption in a Memory Vishwani D. Agrawal.

Nov. 29, 2005ELEC Power Minimization Using Voltage Reduction and Parallel Processing By Sudheer Vemula.

Chung-Kuan Cheng†, Andrew B. Kahng†‡,

Fall 2006, Oct. 5 ELEC / Lecture 8 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Glitch-Free ASICs and Custom.

11/29/2007ELEC Class Project Presentation1 LOW VOLTAGE OPERATION OF A 32-BIT ADDER USING LEVEL CONVERTERS Mohammed Ashfaq Shukoor ECE Department.

1 32-bit parallel load register with clock gating ECE Department, 200 Broun Hall, Auburn University, Auburn, AL 36849, USA Lan Luo ELEC.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

©2010 Cengage Learning Engineering. All Rights Reserved.10-0 Introduction to VHDL PowerPoint Presentation © Cengage Learning, Engineering. All Rights.

9/27/05ELEC / Lecture 91 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Computation Energy Randy Huang Sep 29, Outline n Why do we care about energy/power n Components of power consumption n Measurements of power consumption.

Low power architecture and HDL coding practices for on-board hardware applications Kaushal D. Buch ASIC Engineer, eInfochips Ltd., Ahmedabad, India

EE466: VLSI Design Power Dissipation. Outline Motivation to estimate power dissipation Sources of power dissipation Dynamic power dissipation Static power.

156 / MAPLD 2005 Rollins 1 Reducing Energy in FPGA Multipliers Through Glitch Reduction Nathan Rollins and Michael J. Wirthlin Department of Electrical.

ELEC 6270 Low power design of Electronic Circuits Advisor: Dr.Vishwani Agrawal Student: Chaitanya Bandi.

Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style Sumeer Goel, Ashok Kumar, and Magdy A. Bayoumi.

ICCAD 2003 Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level Yuvraj.

1 VLSI Design SMD154 LOW-POWER DESIGN Magnus Eriksson & Simon Olsson.

Slide: 1International Conference on Electronics, Circuits, and Systems 2010 Department of Electrical and Computer Engineering University of New Mexico.

Mehdi Sadi, Italo Armenti Design of a Near Threshold Low Power DLL for Multiphase Clock Generation and Frequency Multiplication.

32-BIT ADDER FOR LOW VOLTAGE OPERATION WITH LEVEL CONVERTERS PRIYADHARSHINI S.

Power Reduction for FPGA using Multiple Vdd/Vth

Team MUX Adam BurtonMark Colombo David MooreDaniel Toler.

POWER-DRIVEN MAPPING K-LUT-BASED FPGA CIRCUITS I. Bucur, N. Cupcea, C. Stefanescu, A. Surpateanu Computer Science and Engineering Department, University.

Review: Basic Building Blocks  Datapath l Execution units -Adder, multiplier, divider, shifter, etc. l Register file and pipeline registers l Multiplexers,

Logic Synthesis for Low Power(CHAPTER 6) 6.1 Introduction 6.2 Power Estimation Techniques 6.3 Power Minimization Techniques 6.4 Summary.

Washington State University

DCSL & LVDCSL: A High Fan-in, High Performance Differential Current Switch Logic Families Dinesh Somasekhaar, Kaushik Roy Presented by Hazem Awad.

Teaching VLSI Design Considering Future Industrial Requirements Matthias Hanke

Optimal digital circuit design Mohammad Sharifkhani.

Advanced VLSI Design Unit 06: SRAM

26 th International Conference on VLSI January 2013 Pune,India Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages Vijay.

MICAS Department of Electrical Engineering (ESAT) Design-In for EMC on digital circuit December 5th, 2005 Low Emission Digital Circuit Design Junfeng Zhou.

1 KU College of Engineering Elec 204: Digital Systems Design Lecture 11 Binary Adder/Subtractor.

Bootstrapped Full-Swing CMOS Driver for Low Supply Voltage Operation Speaker ： Hsin-Chi Lai Advisor ︰ Zhi-Ming Lin National.

Digital to Analog Converters (DAC) 2 ©Paul Godin Created March 2008.

Supply Voltage Biasing Andy Whetzel and Elena Weinberg University of Virginia.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Under-Graduate Project Improving Timing, Area, and Power Speaker: 黃乃珊 Adviser: Prof.

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University

Spring 2010, Mar 10ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2010 Gate Sizing Vishwani D. Agrawal James J. Danaher.

Basics of Energy & Power Dissipation

Bi-CMOS Prakash B.

By: C. Eldracher, T. McKee, A Morrill, R. Robson. Supervised by: Professor Shams.

A Method for Reducing Active and Leakage Power in Kogge-Stone Adder VLSI Design – ECE6332 Elaheh Sadredini Luonan Wang December 02, 2014.

ELEC Digital Logic Circuits Fall 2015 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering.

M V Ganeswara Rao Associate Professor Dept. of ECE Shri Vishnu Engineering College for Women Bhimavaram Hardware Architecture of Low-Power ALU using Clock.

Very low voltage 16-bit counter in high leakage static CMOS technology

Reduced Voltage Test Can be Faster!

ELEC 6970: Low Power Design Class Project By: Sachin Dhingra

Digital Integrated Circuits CMOS I: Static Characteristics

Power Reduction Technique

Presentation transcript:

December 1, 2005 ELEC Project Presentation 1 Dual-Voltage Supply for Power Reduction ELEC 6970 – Low Power Design Project Presentation by Muthubalaji Ramkumar

December 1, 2005ELEC Project Presentation2 Problem Statement To Use a dual-supply voltage in order to reduce the power consumption of the 32 x 32 bit integer array multiplier circuit without compromising the overall delay To Use a dual-supply voltage in order to reduce the power consumption of the 32 x 32 bit integer array multiplier circuit without compromising the overall delay

December 1, 2005ELEC Project Presentation3 Power and Delay Power → Power → V DD 2 Delay → Delay → KV DD ─────── (V DD – V t ) α

December 1, 2005ELEC Project Presentation4 Approach  Low Voltage Assignment to as many cells as possible  The interconnections in this multiplier circuit makes it difficult  Therefore assign Low Voltage Supply to as many gates as possible

December 1, 2005ELEC Project Presentation5 Things to watch  Reducing the Voltage Supply will increase the delay of a gate  Therefore assign Low-Voltage Supply only to the gates which do not have any influence on the Critical Path Delay directly or indirectly  Low voltage gate should have adequate voltage swing in order to drive a High Voltage gate its feeding in to.

December 1, 2005ELEC Project Presentation6 4 x 4 Multiplier

December 1, 2005ELEC Project Presentation7 Multiplier Cell

December 1, 2005ELEC Project Presentation8 Low-Voltage Supply Assignment Output Cells along the edge N-1G4 First Row 3(N-1)G1,G2,G3 Second Row to Last Row N(N-1)G1 Left Column 2(N-1)G2,G3

December 1, 2005ELEC Project Presentation9  Total Number of gates = 6N 2  Number of gates with Low Voltage assignment = (N-1)(N+6) assignment = (N-1)(N+6)  Percentage of the circuit with Reduced V DD =(N-1)(N+6) / 6N 2

December 1, 2005ELEC Project Presentation10 Percentage of the Circuit with Reduced Voltage Supply

December 1, 2005ELEC Project Presentation11 Experimental Results for a Cell Voltage (Volts) P dyn (Microwatts) P static (Picowatts) Delay(Sec) p p p n

December 1, 2005ELEC Project Presentation12 Experimental Results for a 4 x 4 Multiplier Voltage (Volts) P dyn (Microwatts) P static (Nanowatts) Delay(Sec) n n n n

December 1, 2005ELEC Project Presentation13 A Single Inverter Voltage (Volts) P dyn (Microwatts) P static (Picowatts) Delay(Sec) p p p p

December 1, 2005ELEC Project Presentation14 4 x 4 bit array Multiplier  N=4   Total Number of Gates = 6N 2 = 6(16) = 96  Number of Gates with Low V DD = (N-1)(N+6) = (3)(10) = 30 = % = (3)(10) = 30 = %  Number of Gates with Normal V DD = 96 – 30 = 66 = 68.75% 96 – 30 = 66 = 68.75%

December 1, 2005ELEC Project Presentation15 Power Estimation  Using Dual-Voltages, 1.8V & 1.5V Power Consumption = (0.3125)(132.1uW) + (0.6875)(213uW) = uW  12% Power Reduction

December 1, 2005ELEC Project Presentation16 Power Estimation  Using Dual-Voltages, 1.8V & 1.2V Power Consumption = (0.3125)(75.8uW) + (0.6875)(213uW) = uW  % Power Reduction

December 1, 2005ELEC Project Presentation17 32 x 32 bit array Multiplier  N=32   Total Number of Gates = 6N 2 = 6(1024) = 6144  Number of Gates with Low V DD = (N-1)(N+6) = (31)(38) = 1178 = 19.2 % = (31)(38) = 1178 = 19.2 %  Number of Gates with Normal V DD = 6144 – 1178 = 4966 = 80.8% 6144 – 1178 = 4966 = 80.8%

December 1, 2005ELEC Project Presentation18 Power Estimation  Using Dual-Voltages, 1.8V & 1.5V Power Consumption = (0.192)(8.45mW) + (0.808)(13.63mW) = mW  7.3% Power Reduction

December 1, 2005ELEC Project Presentation19 Power Estimation  Using Dual-Voltages, 1.8V & 1.2V Power Consumption = (0.192)(4.85mW) + (0.808)(13.63mW) = 11.9 mW  12.4% Power Reduction

December 1, 2005ELEC Project Presentation20 Conclusion Pros…  Reduction in power  Delay is not compromised  No change in Area  Dual-power supply is easy to generate using potential dividers Cons…  The percentage of the circuit that can be fed with Low Voltage supply is less  Requires careful assignment of Low Voltage Supply

December 1, 2005ELEC Project Presentation21 Comments  Learnt VHDL basics  Introduction to very useful EDA tools  Get a feel of VLSI Design  Appreciation of Low Power Design  Time Consuming but worth it