Beyond the Red Brick Wall: Physical Design Challenges at 50nm and Below Andrew B. Kahng UC San Diego, Depts. of CSE and ECE ( )

2 ASPDAC’2001 What is NOT a Physical Design Challenge?  Problems that are beyond PD scope / control Finding high-k dielectric materials Finding high-k dielectric materials Creativity (e.g., AMS/RF circuit innovations) Creativity (e.g., AMS/RF circuit innovations) t We are in the “automation” (not the creativity) business  Problems whose instance sizes and solution times scale with power of available computing platforms Most analyses (static timing, SI, dynamic simulation, …) Most analyses (static timing, SI, dynamic simulation, …) t Assumption: “methodology” will be applied (filtering, incr / ECO, hierarchy, divide/conquer, abstracts, guardbanding, …) In future, commodity syntheses In future, commodity syntheses t Scalable Engines = (free) Commodities t (multilevel paradigm:) Place, Perf Opt, Logic Synth, Route, …

3 ASPDAC’2001 Primary Driver at 50nm: System Cost  NRE Cost for Design  TAT = driver for Methodology u  Cost of Design Technology = not so well- understood t Application-Specific CAD (e.g., high-volume custom vs. SOC) t Design Technology Productivity: Roadmaps, Reuse, Metrics u IEEE Design and Test Special Issue, Nov-Dec 2001; ITRS-2001 effort  NRE Cost for Manufacturing  Manufacturing Cost  Design for Cost-of-Manufacturing t Variability and Die-Package-Board interactions

4 ASPDAC’2001 Complementary Driver at 50nm: System Value  Quality of Design = Value of Design Speed, Reliability, Parametric Yield, … Speed, Reliability, Parametric Yield, … Key Issue #1: Power Key Issue #1: Power t Speed-power = fundamental tradeoff t Static power dissipation, power distribution, … u How to avoid battery weight, use of advanced forced-air and chilling, … Key Issue #2: Synchronization and Global Signaling Key Issue #2: Synchronization and Global Signaling t Fundamental clocking limits, latency-insensitive design methodology, …  Issues that are NOT driving PD: “Litany” UDSM = T+SI+IR+GB+L+EM+SH+HE+EMI+SEU…” “Litany” UDSM = T+SI+IR+GB+L+EM+SH+HE+EMI+SEU…”

5 ASPDAC’ TAT: Closing the Synthesis-Analysis Loop  How we handle this loop == the heart of “methodology” t E.g., “Correct by Construction” (assume/enforce, predict/enforce, …) t E.g., “Construct by Correction” (tool, data model, DB for tight S/A loop) t Syntheses must have true estimation capabilities  Syntheses must be driven by most-appropriate abstractions or approximations of Analyses  How much is left on the table depends on two things: How well do we make methodology choices? (Space / shield / rpt / size …? Optimization / layout / synthesis loop structure?) How well do we make methodology choices? (Space / shield / rpt / size …? Optimization / layout / synthesis loop structure?) How well do we identify objectives for engines in PD? (e.g., FP, GPlace) How well do we identify objectives for engines in PD? (e.g., FP, GPlace) Greatest leverage: Chip planning (block shaping/placement, interconnect planning) Greatest leverage: Chip planning (block shaping/placement, interconnect planning)  Very important to work on right problems with right goals Cf. ISPD-2000 talk on floorplanning Cf. ISPD-2000 talk on floorplanning

6 ASPDAC’ Cost: Closing the Design-Manufacturing Loop  Silicon mindset  ECAD / Mask / Mfg merged infrastructures  Variability: improved taxonomy and criteria

7 ASPDAC’2001 What does EDA know about process today? Process Develop.: Lithography Device Device models Design rules TCAD Design ECAD GDSII “Clean Abstraction” = As Little as Possible = Next to Nothing

8 ASPDAC’2001 What Must EDA Know Tomorrow? Mask Process Develop.: Lithography Device Device models Design rules TCAD Production Fab Design Process Requirements Devl. Fab ECAD Semi suppliers GDSII, tolerances,... tolerances... “Useful Abstraction” = As Much as Possible

9 ASPDAC’2001 PSM in 180nm Library Cell

10 ASPDAC’2001 Field-Dependent Aberration  Field-dependent aberrations cause placement errors and distortions Center: Minimal Aberrations Edge: High Aberrations Towards Lens Wafer Plane Lens R. Pack, Cadence

11 ASPDAC’2001 Example Challenges  Function-aware OPC/PSM/Fill insertion (corrections) Layout corrections are for predictable circuit performance, function Layout corrections are for predictable circuit performance, function Tools should understand functional intent, make only the corrections that win $$$, reduce performance variation Tools should understand functional intent, make only the corrections that win $$$, reduce performance variation Applies to mask inspection also Applies to mask inspection also  Cost-aware corrections Don’t make corrections that can’t be manufactured or verified Don’t make corrections that can’t be manufactured or verified Understand costs of each correction (data volume, yield costs, verification costs, etc.) Understand costs of each correction (data volume, yield costs, verification costs, etc.)  Solutions to (difficult) flow issues how to avoid making same correction 3x (lib, router, PV tool) how to avoid making same correction 3x (lib, router, PV tool)

12 ASPDAC’2001 Some Variability Analysis Needs Taxonomy: Taxonomy: t Static: t_ox, V_t, L_eff, … t Dynamic: V_dd, rho, … t Instance: interconnection topology and embedded length distribution, … t Correctable vs. uncorrectable Distinguish primary vs. derived variabilities, e.g., dopant / Idsat Distinguish primary vs. derived variabilities, e.g., dopant / Idsat Model back to root causes, e.g., registration error, microloading Model back to root causes, e.g., registration error, microloading Model the context, e.g., vias, dielectrics, critical paths Model the context, e.g., vias, dielectrics, critical paths Model correlations and anti-correlations (e.g., dimensions of line vs. space, line vs. ILD) Model correlations and anti-correlations (e.g., dimensions of line vs. space, line vs. ILD)

13 ASPDAC’ Closing the Design Technology Productivity Gap  Design Productivity Gap huge cost to semiconductor industry  huge cost to semiconductor industry  Traditional perspective: change the Design Problem, invent new algorithms,...  New perspective: Design Productivity Gap == Design Technology Productivity Gap Problem: Improve Time-To-Market and Quality-of-Result for Design Technology Problem: Improve Time-To-Market and Quality-of-Result for Design Technology New goal: Improve how we specify, develop, and measure and improve Design Technology (PD is a good place to start) New goal: Improve how we specify, develop, and measure and improve Design Technology (PD is a good place to start)

14 ASPDAC’2001 Aspects of the Design Technology Gap  No Roadmap  Time-to-Market: 5-7 yr to get new algorithm into production Time-to-Market: No reuse in design technology Lack of “Foundation CAD-IP” Lack of “Foundation CAD-IP” Over-resourcing of non-strategic technology Over-resourcing of non-strategic technology  QOR: difficult to evaluate impact of new tools, new research on overall design process  Lack of standard metrics (especially cost metrics) for design technology, design process If you can’t measure it, you can’t improve it !!! If you can’t measure it, you can’t improve it !!!

15 ASPDAC’2001 New Infrastructure is Needed to Answer:  Improved vision and design technology planning (“specify”): t What will the design problem look like? t Accurate roadmapping for Design Technology t Application-Specific Design Technology (cost-driven)  Improved execution (“develop”): t How can we quickly develop the right technology (TTM)? t Reusable, commodity, Foundation CAD-IP  Improved measurement (“measure and improve”): t Did we solve the problem (QOR)? Did the design process improve? t Design tool/process metrics, design process instrumentation  Design Technology Productivity will improve Design Productivity

16 ASPDAC’2001 Optical Proximity Correction (OPC)  Corrective modifications to improve process control improve yield (process latitude) improve yield (process latitude) improve device performance improve device performance With OPC No OPC Original Layout OPC Corrections

17 ASPDAC’2001 Macroscopic Process Effects CMP, SOG RIE CVD Dummy Fill controls several types of process distortions : R. Pack, Cadence

18 ASPDAC’2001 Direction for Development - PSM  New logic (mapping) and performance optimization formulations with phase shifting, gate lengths and wire widths continuously variable between b and B with phase shifting, gate lengths and wire widths continuously variable between b and B without phase shifting, gate lengths and wire widths must be at least B without phase shifting, gate lengths and wire widths must be at least B not all features can be phase-shifted: function-driven not all features can be phase-shifted: function-driven What is optimal choice of phase-shifted features, and their sizes?

19 ASPDAC’2001 Direction for Development - PSM  Understand PSM implications for custom layout define a taxonomy of phase conflict define a taxonomy of phase conflict no set of traditional design rules can handle all phase conflicts  what are “good layout practices”? no set of traditional design rules can handle all phase conflicts  what are “good layout practices”? t “no T’s on poly” t “fingered transistors should have even-length fingers” t etc.  Address PSM as a multi-layer problem e.g., conflict can be solved by re-routing a connection to another layer e.g., conflict can be solved by re-routing a connection to another layer

20 ASPDAC’2001 Directions for Development – Pattern Fill  Practical criteria No cleavage lines; Probeability; Multiple length scales; Simultaneous control of fill area/perimeter; etc. No cleavage lines; Probeability; Multiple length scales; Simultaneous control of fill area/perimeter; etc.  Hierarchical filling  Grounded fill generation  Multi-layer density control  RCX/TA flows (with P&R)