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3 8 modules--perform I/O “housekeeping” functions use in project: example VHDL package—UP3pack.vhd modules must be “visible” in your path or included in your design in some way (directly, package, etc.)

4 output input

5 power VGA port parallel port PS2 port +3.3V supply LED on/off switch user-definable pushbuttons user-definable LEDs user-definable DIP switches global reset USB port serial port invalid input voltage LED UP3 BOARD and FLASH SRAM Cyclone chip +5V supply LED LC Display

6 COMPONENT LCD_Display PORT (Hex_Display_Data: IN STD_LOGIC_VECTOR (Num_Hex_Digists*4)-1 DOWNTO 0; reset, clock_48MHz: IN std_logic; LCD_RS, LCD_E: OUT STD_LOGIC; DATA_BUS: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); END COMPONENT; input 4 bits hex digit signal values to convert to ASCII hex digits and send to LED display (note: Appendix D contains ASCII to hex table) Num_Hex_Digits is a Generic parameter which can be given a value in a VHDL file or in a schematic (16 characters, 2 lines available) OutputsPIN (important!) LCD_RS108 LCD_E 50 LCD_RW 73 DATA_BUS (7 DOWNTO 0):113, 106, 104, 102, 100, 98, 96, 94

7 COMPONENT Debounce PORT (pb, clk_100Hz:IN STD_LOGIC; pb_debounced:OUT STD_LOGIC); END COMPONENT; pb is the input from a pushbutton (see I/O pins, chapter 2) since pushbuttons have a mechanical “bounce”, this component samples the input over several clock cycles and filters out the bounces; it will register the pushbutton input only when several sequential samples of the input agree the clock input is used by the bounce filter (see example below) when “push” is registered, output goes low: it remains low until button is released

8 COMPONENT OnePulse PORT (PB_debounced, clock:IN STD_LOGIC; PB_single_pulse:OUT STD_LOGIC); END COMPONENT; after the push button signal is “debounced”, this component can be used to ensure that the output read from the pushbutton is high for only one clock cycle, no matter how long the pushbutton is held down this is useful for building finite state machines--an edge-triggered flip-flop can be used to build a state and each input will be active for only one clock cycle the “clock” input is the clock signal being used to drive the state machine

9 COMPONENT Clk_Div PORT (clock_48MHz: IN STD_LOGIC; clock_1MHz, clock_100KHz, clock_10KHz, clock_1KHz, clock_100Hz, clock_10Hz, clock_1Hz: OUT STD_LOGIC) END COMPONENT; the input is from the (48MHz) on-board clock (pin 29 for the Cyclone chip); JP3 jumper must be set to select the 48MHz USB—this the default setting the outputs are clock signals of various frequencies which can be used in designs Note: actual frequency will be (listed frequency)*( /-.005%)

10 Example: Debounce Clock (pin 29) OnePulse fsm Clk_Div Clock_100Hz Clock_1MHz pushbutton

11 COMPONENT Mouse PORT ( clock_48Mhz,reset: IN STD_LOGIC; mouse_data, mouse_clk:INOUT STD_LOGIC; left_button,right_button: OUT STD_LOGIC; mouse_cursor_row,mouse_cursor_column: OUT STD_LOGIC_VECTOR(9 DOWNTO 0); END COMPONENT; the input is from the (48MHz) on-board clock (pin 29 for the Cyclone chip); mouse_data is pin 13, mouse_clk is pin 12: BIDIRECTIONAL (also used for keyboard) cursor outputs give postion in 640 x 480 pixel screen (VGA); cursor is initialized to the middle of the screen button outputs are high when the corresponding button is pushed

12 COMPONENT Keyboard PORT ( keyboard_clk,keyboard_data, clock_48Mhz, reset, read: IN STD_LOGIC; scan_code: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); scan_ready: OUT STD_LOGIC); END COMPONENT; Reads PS/2 keyboard scan code; converts serial data from keyboard to parallel clock input is from the (48MHz) on-board clock (pin 29 for the Cyclone chip); keyboard_data is pin 13, keyboard_clk is pin 12: INPUTS (also used for mouse) read clears the scan_ready signal; reset clears flip-flops for serial-to-parallel conversion scan_code: table of values in Table 11.3; --”make” code: key is hit; “break” code: key is released ex: ‘A’ make = 1C, break = F01C: ‘shift’ make = 12, break = F012 (if key is held down, several makes will be sent before a break) scan_ready goes high when new scan code is sent and can be used to make sure each scan code is read only once

13 COMPONENT VGA_Sync PORT (clock_48MHz, red, green, blue: IN STD_LOGIC; red_out, green_out, blue_out, horiz_sync_out, vert_sync_out: OUT STD_LOGIC; pixel_row, pixel_column: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); END COMPONENT; clock_48MHz signal must come from pin 29 (Cyclone chip) user logic generates the input “color” (red, green, blue) Cyclone chip:horiz_sync --> pin 226, vert_sync --> pin 227 red_out --> pin 228, green_out --> pin 122, blue_out --> pin 170 pixel_row and pixel_column give the pixel address how many colors are available? how many pixels? (“dithering”: one color on odd cycles, different on even  twice as many colors example: pattern sent (even/odd cycles) pattern observed

14 COMPONENT Char_ROM PORT (clock: IN STD-logic; character_address: IN STD_LOGIC_VECTOR (5 DOWNTO 0); font_row, font_col: IN STD_LOGIC_VECTOR (2 DOWNTO 0); row_mux_output: OUT STD_LOGIC); END COMPONENT; generates text for a video display--each character requires an 8 x 8 pixel pattern (see codes, table 9.1--a memory initialization file, tcgrom.mif, is provided; the font data can be stored in one M4K memory block) character_address addresses the character to be displayed font_row and font_col step through the 64 pixels (8x8) needed to display one character Clock loads the address register and should be tied to the video pixel_clock row_mux_output is the pixel value to be output for this character at this position and can be used to generate the correct RGB pixel color

15 How does output occur (examples: chapter 10): monitor contains CRT (cathode ray tube) screen consists of pixels, 640 in a row and 480 in a column (VGA format) “refresh rate”: how quickly these pixels are scanned standard rate is 60 times / second (60 Hz) (human eye can detect “flicker” below 30Hz) if there are 640 X 480 pixels, with a 60Hz refresh rate, how much time is available to scan one pixel? What clock speed is therefore required? What is the onboard clock speed? (note: UP3 has PLL which can be used to obtain faster refresh rates) Sync signals tell when to start a new row or column

16 random number generation (Appendix A): actually generates “pseudorandom” numbers Q: what is the difference? Method: example: n = 32--will give 32-bit pseudorandom sequence of bits from table, read “XOR from bits 32,22,2,1” (bits are 32--1, not 31--0) build a 32-bit shift register that shifts left one bit per cycle next bit to be input into lsb should be the XOR of bits 32,22,2,1 this will generate a sequence in “pseudorandom order” initial value in the register is the “seed”; 0 should not be used (why?)

17 Example: n = 3--table gives bits 3,2 steppattern(bit 3) xor (bit 2) from here, the sequence will repeat we have a sequence of the numbers 1-7: 7,6,4,1,2,5,3 this is the longest nonrepeating sequence we can have order will always be the same, seed only determines where we start

18 How good are the random numbers generated? Reference: Shruthi Narayanan, M.S. 2005, ATI Technologies Hardware implementation of genetic algorithm modules for intelligent systems: Random numbers generated by one shift register Random numbers generated by multiple shift registers