Analysis of a Packet Switch with Memories Running Slower than the Line Rate Sundar Iyer, Amr Awadallah, Nick McKeown Departments of Electrical Engineering & Computer Science, Stanford University

Stanford University 2 Problem Statement Motivation: To design an extremely high speed packet switch.

Stanford University 3 A Multi-Terabit OQ Switch Line Rate OC3072 4XOC Gb/s 1cell/2ns Line Rate OC3072 4XOC Gb/s 1cell/2ns Output Queued Switch

Stanford University 4 Main Problem Buffer Memory Conventional SRAM How to buffer cells in a memory at a rate of 1ns ? Write Rate R 1 cell in 2 ns Read Rate R 1 cell in 2 ns

Stanford University 5 Problem Statement Redefined Motivation: To design an extremely high speed packet switch with memories running slower than the line rate. This talk: I s about the analysis of an obvious approach.

Stanford University 6 Architecture of a PPS Definition: A PPS is comprised of multiple identical lower-speed packet-switches operating independently and in parallel. An incoming stream of packets is spread, packet-by-packet, by a demultiplexor across the slower packet-switches, then recombined by a multiplexor at the output.

Stanford University 7 Architecture of a PPS OQ Switch N=4 R R R R R R R R Multiplexor Demultiplexor Multiplexor (R/k) k=3 1 2 (R/k)

Stanford University 8 Parallel Packet Switch Questions 1.Can it behave like a single big output queued switch? 2.Can it provide delay guarantees, strict- priorities, WFQ, …?

Stanford University 9 Precise Emulation of an OQ Switch OQ Switch R R R R R R R R PPS Yes No =?

Stanford University 10 Layer 1 Layer 2 Layer N=4 R R R R R R R R Emulation Scenario R/3

Stanford University 11 Layer 1 Layer 2 Layer N=4 R R R R 1 3 R R R R Why is there no Choice at the Input ? j j j j 5 j j j j j 4 j j j 5

Stanford University 12 Layer 1 Layer 2 Layer N=4 R R R R 1 3 R R R R Result of no Choice j j 54

Stanford University 13 How does one Increase Choice ? Speedup Layer 1 Layer 2 Layer N=4 R R R R 1 3 R R R R 2 1 j 1 j 1 j j j j j 5 j j 1 4 j j j j (2R/3)

Stanford University 14 Effect of Speedup on Choice R A speedup of S= 2, with k= 10 links 2R/k Layer 1 Layer 10 Layer 2 Layer 9

Stanford University 15 Definition Available Input Link Set (AIL) AIL(i,n) is the set of layers to which external input port i can start writing a cell to, at time slot n.

Stanford University 16 Definition Departure Time of a Cell (n’) The departure time of a cell, n’, is the time it would have departed from an equivalent FIFO OQ switch.

Stanford University 17 Definition Available Output Link Set (AOL) AOL(j,n’) is the set of layers that output j can start reading a cell from, at time slot n’.

Stanford University 18 Main Observation Layer 1 Layer 2 Layer N=4 R R R R 1 3 R R R R j j j j 2 3 (2R/3) Inputs can only send to the AIL set. Outputs can only read from the AOL set. 5 1 j j j 222

Stanford University 19 Minimum size of AIL, AOL: |AIL|,>= Total – Maximum number of |AOL|links links which can have cells in progress Lower Bounds on Choice Sets = k - ( k/S - 1 )

Stanford University 20 Assurance of Choice A cell must be sent to a link which belongs to both the AIL and the AOL set.

Stanford University 21 Parallel Packet Switch Results If S > 2k/(k+2)  2 then each cell is guaranteed to find a layer that belongs to both the AIL and AOL sets. If S > 2k/(k+2)  2 then a PPS can precisely emulate a FIFO output queued switch for all traffic patterns.

Stanford University 22 Precise Emulation of an OQ Switch OQ Switch R R R R Yes No R R R R PPS =?

Stanford University 23 Parallel Packet Switch Results If S > 3k/(k+3)  3 then a PPS can precisely emulate an OQ switch with WFQ or strict priorities for all traffic patterns.

Stanford University 24 Is this Practical ? NO There are two reasons: 1) Maintaining AIL - That is easy. AOL - That is not. 2) Packet order is decided by the output.

Stanford University 25 A Practical Distributed Algorithm If S > 2k/(k+2)  2 then a PPS with distributed AOL can precisely emulate a FIFO output queued switch for all traffic patterns. The PPS will have a fixed latency of Nk/S time slots.

Stanford University 26 Conclusions –Its possible to design a high speed single stage packet switch from multiple slower speed packet switches. –Such a switch can emulate an OQ switch. –There remain a couple of open questions Making QoS practical. Making multicasting practical. –This is just the first step towards scaleable switch fabrics.