Look Up Machine Mid Semester Presentation Chanit Giat Rachel Stahl Instructor: Artyom Borzin הטכניון - מכון טכנולוגי לישראל המעבדה למערכות ספרתיות מהירות הפקולטה להנדסת חשמל

Suggested Improvements : 2 input FIFO’s 2 input FIFO’s 2 decoders 2 decoders Pipelining decoded instructions Pipelining decoded instructions Parallel access to Bit Map and UTCAM Parallel access to Bit Map and UTCAM Reliability: Reliability: –96 bit representation of data –‘delete’ and ‘set attr.’ access to Bit Map המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

Dividing the machine: The machine will be divided into 2 main stages: up to decoding, and from the execution. The machine will be divided into 2 main stages: up to decoding, and from the execution. The 2 stages will be separated by a FIFO, which will schedule the flow through the machine. The 2 stages will be separated by a FIFO, which will schedule the flow through the machine. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

New Block Diagram: FIFO Input FIFO 0 VBF 0 CRC Input FIFO 1 VBF 1 Decoder1 Decoder0 DBM OutputFIFO המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

Doubling the front end of the machine: Modifying the Data Stream Controller, so it passes the transactions to the FIFO’s – one at a time: Modifying the Data Stream Controller, so it passes the transactions to the FIFO’s – one at a time: –This decision will mainly improve the handling of 2 following “long” ‘search’ commands. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 0 1 !SOT !SOT SOT & !wrfull(1) SOT & !wrfull(0)

OOO considerations: At the beginning, separating the ‘search’ command from the others was considered, but abandoned: At the beginning, separating the ‘search’ command from the others was considered, but abandoned: –Command dependencies: it may work sometimes, but the results will not fit the order in which the commands were sent. –A better performance gain from decoding ‘search’ commands in parallel to each other, than in parallel to other commands. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

Doubling the front end of the machine (cont.) There are 2 options regarding the CRC module: There are 2 options regarding the CRC module: –Doubling the HW Space Space Frequency Frequency –Scheduling the access to the module Effort Effort המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

Doubling the front end of the machine (cont.) Scheduling decoded instructions: additional HW will pass instructions to the DBM Input FIFO from one decoder at a time: Scheduling decoded instructions: additional HW will pass instructions to the DBM Input FIFO from one decoder at a time: –The decision is almost identical to the one before the input FIFO’s: המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

FIFO scheduling FSM 0 1 !dec0_rdy 0’ 1’ !dec1_rdy dec0_rdy & !fifo_full dec1_rdy & !fifo_full Wr_done Wr_done!Wr_done!Wr_done המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

DBM Input FIFO The FIFO schedules the transition between the 2 parts of the machine. The FIFO schedules the transition between the 2 parts of the machine. The packets are different for each instruction: The longest packet is 133 bits long. The packets are different for each instruction: The longest packet is 133 bits long. Additional HW will be needed to divide the signals to the right c-level blocks, at the Issue Logic. Additional HW will be needed to divide the signals to the right c-level blocks, at the Issue Logic. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

133 bits FIFO – possible problems: 133 bits FIFO – possible problems: - space - frequency Possible solution: Possible solution: –Transferring the fields in 2/3 stages, each 64 bits long Need for extra HW to reorganize the fields. Need for extra HW to reorganize the fields. DBM Input FIFO המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

Search command flow – present algorithm Calculate 64bit CRC value for the received data Query CAT for entry with [Site#, CRC] Found Insert new record to CAT and AT Successf ul Return PATH and Status Return ErrorReturn PATH and Status No Yes Find the next empty place in CAT המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

Parallel access to Bit Map and UTCAM המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory ADDBlock Index Register Index Register Bit Map Unit Valid_index ack exunit

Calculate 64bit CRC value for the received data Query CAT for entry with [Site#, CRC] Found Insert new record to CAT and AT Successf ul Return PATH and Status Return ErrorReturn PATH and Status No Yes Find the next empty place in CAT Search command flow – new algorithm המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

Reliability Issues: Will be implemented if schedule allows. Will be implemented if schedule allows. Suggested changes do not contribute to throughput. Suggested changes do not contribute to throughput. Delete and Set_Attr access to valid indexes can be under the OS responsibility. Delete and Set_Attr access to valid indexes can be under the OS responsibility. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

schedule 1 week: tools, study code 1 week: tools, study code 4-6 weeks: design (best case) 4-6 weeks: design (best case) 2 weeks: debug + performance check 2 weeks: debug + performance check המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

The fields transferred by the decoder: CID – 5 bits. CID – 5 bits. AsIs – 32 bits. AsIs – 32 bits. Site – 32 bits. Site – 32 bits. Path – 21 bits. Path – 21 bits. ttl, weight – 16 bits each. ttl, weight – 16 bits each. CRC – 64 bits. CRC – 64 bits. Search: CID, AsIs, site and CRC – 133 bits. Search: CID, AsIs, site and CRC – 133 bits. Set_Attr: CID, AsIs, path, ttl & weight – 90 bits. Set_Attr: CID, AsIs, path, ttl & weight – 90 bits. Delete: CID, AsIs & path – 58 bits. Delete: CID, AsIs & path – 58 bits. Count Free & Init: CID & AsIs – 37 bits. Count Free & Init: CID & AsIs – 37 bits. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

Dividing the fields into 70-bit wide FIFO: Search: Search: –CID + site : 37 bits. –CRC: 64 bits. –AsIs: 32 bits. Set_Attr: Set_Attr: –CID + path + ttl + weight : 58 bits. –AsIs: 32 bits. Delete, count free & init can be transferred in one row in the FIFO. Delete, count free & init can be transferred in one row in the FIFO. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

Parallel access to Bit Map and UTCAM Initiation: when initiating the Bit Map Table, init the register to 21’h0. Initiation: when initiating the Bit Map Table, init the register to 21’h0. ADD block: ADD block: –Reads the register, and tries to write to the AT/CAT. –If unsuccessful : nothing happened… –If successful : sets the ack bit. Bit Map Unit: when receiving ack: Bit Map Unit: when receiving ack: –Clears the valid bit. –Marks the current index as taken. –Looks for the next free index, and updates the register. –Sets the valid bit. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory ADDBlock Index Register Index Register Bit Map UnitValid_indexack