Priyadharshini Shanmugasundaram Vishwani D. Agrawal DYNAMIC SCAN CLOCK CONTROL FOR TEST TIME REDUCTION MAINTAINING.

Slides:



Advertisements
Similar presentations
TEST TIME OPTIMIZATION In Scan Circuits Priyadharshini S. Masters Thesis Defense Thesis Advisor: Dr. Vishwani D. Agrawal Committee Members: Dr. Adit D.
Advertisements

Weighted Random and Transition Density Patterns for Scan-BIST Farhana Rashid* Vishwani D. Agrawal Auburn University ECE Department, Auburn, Alabama
1 A Random Access Scan Architecture to Reduce Hardware Overhead Anand S. Mudlapur Vishwani D. Agrawal Adit D. Singh Department of Electrical and Computer.
Power Reduction Techniques For Microprocessor Systems
Minimum Energy CMOS Design with Dual Subthrehold Supply and Multiple Logic-Level Gates Kyungseok Kim and Vishwani D. Agrawal ECE Dept. Auburn University.
Praveen Venkataramani Suraj Sindia Vishwani D. Agrawal FINDING BEST VOLTAGE AND FREQUENCY TO SHORTEN POWER CONSTRAINED TEST TIME 4/29/ ST IEEE VLSI.
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program Tezaswi Raja Vishwani Agrawal Michael L. Bushnell Rutgers University,
Fall 06, Sep 19, 21 ELEC / Lecture 6 1 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic.
Nitin Yogi and Vishwani D. Agrawal Auburn University Auburn, AL 36849
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed Tezaswi Raja, Dept. of ECE, Rutgers University Vishwani D. Agrawal, Dept. of ECE, Auburn.
Dynamic SCAN Clock control In BIST Circuits
Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal
Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock Priyadharshini Shanmugasundaram Vishwani D. Agrawal.
Design of Variable Input Delay Gates for Low Dynamic Power Circuits
11/01/05ELEC / Lecture 171 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
11/17/05ELEC / Lecture 201 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
May 14, ISVLSI 09 Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations Jins Davis Alexander Vishwani.
5/1/2006VTS'061 Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring Vishwani D. Agrawal Auburn University, Dept. of ECE, Auburn,
August 12, 2005Uppalapati et al.: VDAT'051 Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells 9th VLSI Design & Test Symposium.
4/28/05Vemula: ELEC72501 Enhanced Scan Based Flip-Flop for Delay Testing By Sudheer Vemula.
Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA Vishwani D. Agrawal Alok S. Doshi.
Spring 07, Feb 20 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Reducing Power through Multicore Parallelism Vishwani.
Practically Realizing Random Access Scan By Anand Mudlapur ECE Dept. Auburn University.
8/19/04ELEC / ELEC / Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test Fall 2004 Vishwani.
HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT Vishwani D. Agrawal Agere Systems Processor Architectures and Compilers Research Murray Hill, NJ
Practically Realizing Random Access Scan Anand S. Mudlapur Department of Electrical and Computer Engineering Auburn University, AL USA.
8/18/05ELEC / Lecture 11 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
June 10, 20011High-speed test HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT  Available automatic test equipment (ATE) speed is MHz; VLSI chip.
Vishwani D. Agrawal James J. Danaher Professor
An Efficient Test Data Reduction Technique Through Dynamic Pattern Mixing Across Multiple Fault Models 2011 VLSI Test Symposium S. Alampally 1, R. T. Venkatesh.
Aug. 13, 2005Mudlapur et al.: VDAT'051 A Novel Random Access Scan Flip-Flop Design Anand S. Mudlapur Vishwani D. Agrawal (Speaker) Adit D. Singh Department.
HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT Vishwani D. Agrawal Agere Systems Processor Architectures and Compilers Research Murray Hill, NJ
Jan. 2007VLSI Design '071 Statistical Leakage and Timing Optimization for Submicron Process Variation Yuanlin Lu and Vishwani D. Agrawal ECE Dept. Auburn.
March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 1 Nitin Yogi and Dr. Vishwani D. Agrawal Auburn.
1 32-bit parallel load register with clock gating ECE Department, 200 Broun Hall, Auburn University, Auburn, AL 36849, USA Lan Luo ELEC.
Spring 07, Feb 22 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Power Aware Microprocessors Vishwani D. Agrawal.
Architectural Power Management for High Leakage Technologies Department of Electrical and Computer Engineering Auburn University, Auburn, AL /15/2011.
Fall 2006: Dec. 5 ELEC / Lecture 13 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani.
March 6, th Southeastern Symposium on System Theory1 Transition Delay Fault Testing of Microprocessors by Spectral Method Nitin Yogi and Vishwani.
Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 11 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani D. Agrawal.
9/27/05ELEC / Lecture 91 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Spring 07, Jan 30 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 SOC Test Scheduling Vishwani D. Agrawal James.
1 Enhancing Random Access Scan for Soft Error Tolerance Fan Wang* Vishwani D. Agrawal Department of Electrical and Computer Engineering, Auburn University,
Spring 07, Feb 15 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Power Dissipation in VLSI Chips Vishwani D. Agrawal.
By Praveen Venkataramani Vishwani D. Agrawal TEST PROGRAMMING FOR POWER CONSTRAINED DEVICES 5/9/201322ND IEEE NORTH ATLANTIC TEST WORKSHOP 1.
By Praveen Venkataramani Committee Prof. Vishwani D. Agrawal (Advisor) Prof. Adit D. Singh Prof. Fa Foster Dai REDUCING ATE TEST TIME BY VOLTAGE AND FREQUENCY.
Power-Aware SoC Test Optimization through Dynamic Voltage and Frequency Scaling Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal Dept. of Electrical.
Finding Optimum Clock Frequencies for Aperiodic Test Master’s Thesis Defense Sindhu Gunasekar Dept. of ECE, Auburn University Advisory Committee: Dr. Vishwani.
Power Saving at Architectural Level Xiao Xing March 7, 2005.
Adopting Multi-Valued Logic for Reduced Pin-Count Testing Baohu Li, Bei Zhang and Vishwani Agrawal Auburn University, ECE Dept., Auburn, AL 36849, USA.
Copyright Agrawal, 2011ELEC5270/6270 Spr 15, Lecture 71 ELEC 5270/6270 Spring 2015 Low-Power Design of Electronic Circuits Energy Source Design Vishwani.
Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock Sindhu Gunasekar Vishwani D. Agrawal.
PRAVEEN VENKATARAMANI VISHWANI D. AGRAWAL Auburn University, Dept. of ECE Auburn, AL 36849, USA 26 th International.
26 th International Conference on VLSI January 2013 Pune,India Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages Vijay.
Robust Low Power VLSI ECE 7502 S2015 Minimum Supply Voltage and Very- Low-Voltage Testing ECE 7502 Class Discussion Elena Weinberg Thursday, April 16,
By Praveen Venkataramani
A Test Time Theorem and Its Applications Praveen Venkataraman i Suraj Sindia Vishwani D. Agrawal
VLSI Design & Embedded Systems Conference January 2015 Bengaluru, India Few Good Frequencies for Power-Constrained Test Sindhu Gunasekar and Vishwani D.
Copyright Agrawal, 2007ELEC6270 Spring 13, Lecture 101 ELEC 5270/6270 Spring 2013 Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani D. Agrawal.
11/15/05ELEC / Lecture 191 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Power Problems in VLSI Circuit Testing Keynote Talk Vishwani D. Agrawal James J. Danaher Professor Electrical and Computer Engineering Auburn University,
ELEC Digital Logic Circuits Fall 2015 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering.
November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan1 Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns Nitin Yogi.
Characterizing Processors for Energy and Performance Management Harshit Goyal and Vishwani D. Agrawal Department of Electrical and Computer Engineering,
ELEC 7950 – VLSI Design and Test Seminar
July 10, th VLSI Design and Test Symposium1 BIST / Test-Decompressor Design using Combinational Test Spectrum Nitin Yogi Vishwani D. Agrawal Auburn.
Vishwani D. Agrawal James J. Danaher Professor
Reduced Voltage Test Can be Faster!
Vishwani D. Agrawal James J. Danaher Professor
A Random Access Scan Architecture to Reduce Hardware Overhead
Presentation transcript:

Priyadharshini Shanmugasundaram Vishwani D. Agrawal DYNAMIC SCAN CLOCK CONTROL FOR TEST TIME REDUCTION MAINTAINING PEAK POWER LIMIT

05/04/2011VTS’11 2 TESTING OF VLSI CIRCUITS - POWER AND TIME - High circuit activity during test Functional slowdown and high test power dissipation Peak power - Large IR drop in power distribution lines Voltage droop and ground bounce (power supply noise) Reduced voltage slows the gates down (delay fault) Average power - Excessive heating Timing failures Permanent damage to circuit Good chip may be labeled as bad → yield loss

05/04/2011VTS’11 3 TESTING OF VLSI CIRCUITS - POWER AND TIME - Existing solution: Use worst-case test clock rate Keeps highest activity per unit time within specification Keeps average and peak power within specification Results in long test time

05/04/2011VTS’11 4 PROBLEM STATEMENT Reduce test time without exceeding the power specification Proposed solution: Adaptive test clock Use worst-case clock rate when circuit activity is not known Monitor circuit activity and speed up the clock when activity reduces

05/04/2011VTS’11 5 MAIN IDEA Observation: Different sequences of test vector bits consume different amounts of power Conventional test clock frequency is chosen based on maximum test power consumption All test vector bits are applied at the same frequency Test vector bit sequences consuming lower power can be applied at higher clock frequencies without exceeding power budget of the chip

05/04/2011VTS’11 6 SPEEDING UP SCAN CLOCK Clock periods Cycle power Power budget Cycle power Power budget Clock periods

05/04/2011VTS’11 7 A DYNAMIC SCAN ARCHITECTURE

05/04/2011VTS’11 8 DYNAMIC CONTROL OF SCAN CLOCK Monitor number of transitions in scan chain Speed-up scan clock when activity in scan chain is low Number of flip-flops in scan shift register (SSR), N = 8 Number of adjustable clock rates, M = 4 Maximum clock rate, fmax = f

05/04/2011VTS’11 9 CLOCK RATE VS. SSR ACTIVITY N = number of flip-flops in scan shift register (SSR) M = number of adjustable clock rates = 4 in this illustration fmax fmax/2 fmax/3 fmax/4 0 N/4 2N/4 3N/4 N Number of non-transitions counted Clock rate N N/2 N/4 0 SSR transitions per clock

05/04/2011VTS’11 10 ISCAS89 BENCHMARK CIRCUITS Circuit Number of scan flip-flops Number of clock rate steps Test time reduction (%) Area overhead (%) ExperimentTheory s s s s s s s

05/04/2011VTS’11 11 S386: ACTIVITY FOR ONE SCAN-IN Input activity = 25% Time reduction = 22.5%

05/04/2011VTS’11 12 ITC02 BENCHMARK CIRCUITS Circuit Number of scan flip-flops Number of clock rate steps Test time reduction (%) u d d f q p a

05/04/2011VTS’11 13 CONCLUSION Dynamic control of scan clock rate reduces test time without exceeding power specification. Vectors with low average scan-in activity give more reduction in test time. Up to 50% reduction in test time is possible. References: P. Shanmugasundaram, Test Time Optimization in Scan Circuits, Master’s Thesis, Department of ECE, Auburn University, Auburn, Alabama, December P. Shanmugasundaram and V. D. Agrawal, “Dynamic Scan Clock Control in BIST Circuits,” Proc. 43 rd IEEE Southeastern Symposium on System Theory, March , 2011, pp

05/04/2011VTS’11 14 QUESTIONS?