10/20/20081 Lab 6 – More State Machines. Multiple processes.

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10/20/20081 Lab 6 – More State Machines. Multiple processes

10/20/20082 Lab 6 - Mealy Outputs State diagram Ref: Chapter 10, RTL Hardware Design Using VHDL

10/20/20083 Mealy Outputs Revised state diagram (sm2) Y=1 / Y=0 / Y=1

10/20/20084 ASM Chart An algorithm state machine (ASM), is an alternative method for representing an FSM. Although an ASM chart contains the same amount of information as a state diagram, it is more descriptive. It is usually used to specify complex sequence of events and actions needed to implement a control path. An ASM is composed of a network of ASM blocks.

10/20/20085 ASM Block

10/20/20086 ASM Block To reduce clutter, sometimes only the signals that are activated (asserted) are shown in the ASM. Example 1:

10/20/20087 ASM Block Example 2:

10/20/20088 ASM – More examples Example 3:

10/20/20089 ASM – More examples A counter from 0 to 8; ASM representation: