S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 11: Logical Effort (1/2) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’07 Last lecture: delay estimation We calculated Rise and Fall delays Q: What happens if we decide to scale the transistors by factor k?

S. Reda EN160 SP’07 Impact of transistor sizing What happens to delay? Is it the case that increasing the size of the transistor always reduces delay?

S. Reda EN160 SP’07 Impact of sizing in a path C out ×K Less output resistance; increase output capacitance → delay reduces (parasitic delay stays the same) Larger input capacitance → increases delay of previous stage! What is the final outcome? Should we size? By how much?

S. Reda EN160 SP’07 Remember gate design If you decide to increase everything by a factor of k How about an inverter?  12 ps in 180 nm process 40 ps in 0.6  m process Unloaded delay =3RC

S. Reda EN160 SP’07 Expressing delay as a linear model “normalized delay”

S. Reda EN160 SP’07 Summary of linear delay model g: logical effort = ratio between input capacitance of the gate size to the input capacitance of the inverter that would deliver the same current h: electric effort = ratio between load capacitance and the gate input capacitance (sometimes called fanout) p: parasitic delay represents delay of gate driving no load set by internal parasitic capacitance

S. Reda EN160 SP’07 Computing logical effort

S. Reda EN160 SP’07 Computing parasitic delay

S. Reda EN160 SP’07 Example: Ring oscillator Estimate the frequency of an N-stage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay:d = Frequency:f osc =

S. Reda EN160 SP’07 Example: Ring oscillator Estimate the frequency of an N-stage ring oscillator Logical Effort: g = 1 Electrical Effort: h = 1 Parasitic Delay: p = 1 Stage Delay:d = 2 Frequency:f osc = 1/(2*N*d) = 1/4N 31 stage ring oscillator in 0.6  m process has frequency of ~ 200 MHz

S. Reda EN160 SP’07 Example: FO4 Inverter Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay:d =

S. Reda EN160 SP’07 Example: FO4 Inverter Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = 1 Electrical Effort: h = 4 Parasitic Delay: p = 1 Stage Delay:d = 5 The FO4 delay is about 200 ps in 0.6  m process 60 ps in a 180 nm process f/3 ns in an f  m process