Input-Specific Dynamic Power Optimization for VLSI Circuits Fei Hu Intel Corp. Folsom, CA 95630, USA Vishwani D. Agrawal Department of ECE Auburn University, AL 36849, USA October 5, 2006

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany2 Outline Background –Dynamic power dissipation –Glitch reduction –Previous LP model with fixed gate delay –Process-variation-resistant LP model Input-specific optimization –Without process-variation –With process-variation Experimental results Conclusion

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany3 Background Dynamic power dissipation –P dyn = P switching + P short-circuit Switching power dissipation –P switching = 1/2 kC L V dd 2 f clk

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany4 Background Glitch reduction –A important dynamic power reduction technique –Glitch power consumes 30~70% P dyn –Related techniques Balanced delay Hazard filtering Transistor/Gate sizing Linear Programming approach

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany5 Glitch reduction Original circuit Balanced path/ path balancing –Equalize delays of all path incident on a gate –Balancing requires insertion of delay buffers. Hazard/glitch filtering –Utilize glitch filtering effect of gate –Not necessary to insert buffer

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany6 Glitch reduction Transistor/gate sizing –Find transistor sizes in the circuit to realize the delay –No need to insert delay buffers –Suffers from nonlinearity of delay model –large solution space, numerical convergence and global optimization not guaranteed Linear programming approach –Adopts both path balancing and hazard filtering –Finds the optimal delay assignments for gates –Uses technology mapping to map the gate delay assignments to transistor/gate dimensions –Guarantees optimal solution, a convenient way to solve a large scale optimization problem

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany7 Previous LP approach Timing window (t, T) d7d7 T7T7 t7t7 T6T6 t6t6 T5T5 t5t5 Gate constraints: T 7  T 5 + d 7 T 7  T 6 + d 7 t 7 ≤ t 5 + d 7 t 7 ≤ t 6 + d 7 d 7 > T 7 – t 7 Circuit delay constraints: T 11 ≤ maxdelay T 12 ≤ maxdelay Objective: Minimize sum of buffer delays

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany8 Process-variation-resistant optimization Motivation –Gate delay assumed fixed in previous models –Variation of gate delay in real circuits Environmental factors: temperature, V dd Physical factors: process variations –Effect of delay variation Glitch filtering conditions corrupted Power dissipation increases from the optimized value –Our proposal Consider delay variations in dynamic power optimization Only consider process variations (major source of delay variation)

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany9 LP model based on statistical timing Statistical timing model with random variables

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany10 Outline Background –Dynamic power dissipation –Glitch reduction –Previous LP model with fixed gate delay –Process-variation-resistant LP model Input-specific optimization –Without process-variation –With process-variation Experimental results Conclusion

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany11 Input-specific optimization Motivation –Previous LP models guarantee glitch filtering for ANY input vector sequence T i - t i < d i for all gates –Redundancy in optimization Insertion of more buffers Increased overhead in power/area –In reality, gates are under embedded environments Optimization for input vector sequence that is possible for the circuit, e.g., functional vectors Same reduction in power dissipation with lower overheads

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany12 Input-specific optimization Glitch generation pattern –Input vector pair that can potentially generate a glitch –AND gate example: Glitch generation probability P g [ i ] = N g [ i ] / N –Probability glitch-generation pattern occurs at inputs of gate i –Steady state signal values match the pattern

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany13 Input-specific optimization Application to basic LP model w/ fixed gate delay model –Static optimization Only static glitches/hazards considered –Relaxation of constraints Relax glitch filtering constraints where glitches unlikely T i - t i (T i – t i )*  i (T i – t i )*  i < d i Selective relaxation Generalized relaxation

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany14 Input-specific optimization Application to process-variation-resistant LP model based on statistical timing –Static optimization –Relaxation of constraints Selective relaxation Generalized relaxation –Tuning factor Original objective Current objective

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany15 Input-specific optimization Why do we need a tuning factor –Dominating path affects critical delay distribution Can be [1,41] 41 Dominating path 1 1 1

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany16 Outline Background –Dynamic power dissipation –Glitch reduction –Previous LP model with fixed gate delay –Process-variation-resistant LP model Input-specific optimization –Without process-variation –With process-variation Experimental results Conclusion

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany17 Experimental results Experimental procedure –Power estimation Event driven logic simulation Fanout weighted sum of switching activities Monte-Carlo simulation with 1,000 samples of delays under process-variation –Results analysis Un-Opt., unit-delay circuit Opt1, previous basic LP model w/ fixed gate delay Opt2, Process-variation-resistant LP model IS-Opt1, IS-Opt2, Input-specific optimizations

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany18 Experimental results – input-specific optimization Application to “Opt1” (basic LP model), IS-Opt1 Un-OptOpt (w/o proc var.)IS-Opt (input-specific w/o proc) maxdelay Pwr. Delay Buffers Pwr. Delay Buffers c c c c c c c c c c

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany19 Experimental results – input-specific optimization Application to “Opt2” under process-variation, IS-Opt2 under 15% intra-die and 5% inter-die variation Un-opt.Opt2 (statistical proc) IS-Opt2 (input-specific statistical proc) Cir. D Max Nom. Mean Max Dev. No. Nom. Mean Max Dev. No. Pwr. (%) Buf. Pwr. (%) Buf. c c c c c c c c c c

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany20 Experimental results – input-specific optimization Critical delay –Similar performance for “Opt2” and “IS-Opt2” Nominal delay Max. deviation

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany21 Outline Background –Dynamic power dissipation –Glitch reduction –Previous LP model with fixed gate delay –Process-variation-resistant LP model Input-specific optimization –Without process-variation –With process-variation Experimental results Conclusion

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany22 Conclusions Explored a new aspect of low-power optimization for VLSI circuits – –The input-specific Optimization – –Optimizing the circuit for a given input sequence that may be specified for the circuit. Defined the concept of glitch-generation probability – –adaptively relax glitch-filtering constraints Experimental results – –Better solution with fewer delay buffers – –Maintain similar power reduction and delay performance – –Up to 80% and 63% reductions in delay buffers

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany23 Q & A

Backups

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany25 Process and delay variations Process variations –Variations due to semiconductor process V T, t ox, L eff, W wire, TH wire, etc. –Inter-die variation Constant within a die, vary from one die to another die of a wafer or wafer lot –Intra-die variation Variation within a die Due to equipment limitations or statistical effects in the fabrication process, e.g., variation in doping concentration Spatial correlations and deterministic variation due to CMP and optical proximity effect

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany26 Delay model and implications Random gate delay model – –Truncated normal distribution –Assume independence –Variation in terms of σ/D nom,i ratio Effect of inter-die variations –Depends on its effect to switching activities – –Definition of glitch-filtering probability P glt = P {t 2 -t 1 < d} Signal arrival time t 1, t 2 Gate inertial delay d – hange of P glt due to inter-die variation –Theorem 1 states the c hange of P glt due to inter-die variation erf(), the error function k, a path and gate dependent constant σ/D nom,i ratio for inter-die variations r, σ/D nom,i ratio for inter-die variations

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany27 Delay model and implications Process-variation-resistant design –Can be achieved by path balancing and glitch filtering –Critical delay may increase Theorem 2 states that a solution is guaranteed only if circuit delay is allowed to increase Proved by example, assuming 10% variation

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany28 LP model based on statistical timing Statistical timing model with random variables

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany29 LP model based on statistical timing Minimum-maximum statistics – needed for tb i, Tb i –Previous works Min, Max for two normal random variable not necessarily distributed as normal Can be approximated with a normal distribution Requiring complex operations, e.g., integration, exponentiation, etc. –Challenges for LP approach Require simple approximation w/o nonlinear operations Our approximation for C=Max(A,B), A, B, and C are Gaussian RVs

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany30 LP model based on statistical timing Min-Max statistics approximation error –Negligible when |  A -  B |> 3(σ A + σ B ) –Largest when  A =  B

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany31 LP model based on statistical timing Variables –Timing, delay variables with mean  and std dev σ –Auxiliary variables, Constraints –Gate constraints Timing window at the inputs for a two-input gate i Timing window at outputs

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany32 LP model based on statistical timing Constraints –Gate constraint Linear approximation – k  [0.707, 1]; choose k=0.85, since –Glitch filtering constraints –Circuit delay constraint

Oct. 5, 2005 Fei Hu, ISLPED 2006, Tegernsee, Germany33 LP model based on statistical timing Parameter –r, σ/D nom,i ratio –D max, circuit delay parameter – , optimism factor  =1, no relaxation  <1, optimistic about the actual glitch width  =0, reduce to previous model Objective –Minimize #buffer inserted – sum of buffer delays