The Design Process CPSC 321 Computer Architecture Andreas Klappenecker.

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Presentation transcript:

The Design Process CPSC 321 Computer Architecture Andreas Klappenecker

Administrative Issues October 10, project deadline October 17, midterm exam Office hours Klappenecker TW 2:00pm-3:00pm Bhojwani M 10:00-11:00am, T 1:00-2:00pm Goyal W 2:00-4:00pm

Levels of Abstraction Specification Architectural Description Verilog, VHDL, ELLA or other HDLs Logic Design Gates and Registers Circuit Design Transistors sized for power and speed Technology mapping Layout

Levels of Abstraction + n+ S G D System Module Gate Circuits Device

MOS Transistors PMOS transistor like a switch ON if gate is 1 OFF if gate is 0 NMOS transistor OFF if gate is 1 ON if gate is 0 Drain (+) Drain (-) Source (+) Source (-) Current Flow

CMOS Circuits Simple Avoids difficulties Resilient Energy efficient Current flow only during switching time

Circuit Design Layering and Fabrication Layout

Hardware Description Languages Abstracting from circuits Structural description Specify full adder by NAND and NOR gates Behavioral description Specify full adder by functional behavior Improves productivity Natural for Computer Scientists

Verilog Structural description Gates, wires, input/output Hierarchical description possible (define full adder in terms of gates) Behavioral description Abstract formulation Functional relationships

Structural Verilog Example module mux(f, a,b,sel); output f; input a,b,sel; wire f1, f2; not(nsel, sel); and(f1, a,nsel); and(f2, b, sel); or (f, f1, f2); endmodule b a sel f

Behavioral Verilog Example module mux2(f, a,b,sel); output f; input a,b,sel; assign f = (a & ~sel) | (b & sel); endmodule

Another Example module mux2(f, a,b,sel); output f; input a,b,sel; reg f; or b or sel) if (sel==1) f = b; else f = a; endmodule

Synthesis Compilation Verilog code is translated into a network of logic gates Optimization Try to find a better solution by logic optimization (limited success) Technology mapping Physical design

Logic Gates and(y, a, b) or(y, a, b) not(y, a) xor(y, a,b) nand(y, a, b) …

Modules module mod_name (parameters); input … output … reg … …… endmodule

Full Adder module fulladd(cin, x, y, s, cout) input cin, x, y; output s, cout; assign s = x ^ y ^ cin; assign cout = (x & y) | (cin & x) | (cin & y); endmodule

Full Adder module fulladd(cin, x,y,s, cout); input cin, x, y; output s, cout; assign { cout, s } = x + y + cin; Endmodule The assign statement sets cout to MSB and s to LSB

Conclusions Verilog will be the language for our next projects Verilog compilers are freely available Programming in a HDL differs from software programming Higher level of abstraction allows to develop large circuits