1 Variability Characterization in FPGAs Brendan Hargreaves 10/05/2006

2 Goals To characterize the physical variability inherent in FPGAs using actual physical measurement –No dependency on simulation –No statistical guessing games Build a variation map to show comparative speeds of logic blocks Test an optimized layout considering process variation versus a generic place and route algorithm

3 Test Equipment Large die, low speed graded FPGAs Low speed grade increases probability of having slow logic blocks Large die increases probability of intra-die variation Altera Cyclone II and Stratix II

4 Experimental Method Ring Oscillators placed at various places on FPGA Measuring frequency in relation to clock Repeating to characterize a new set of logic blocks odd number of stages

5 Logic Block (Cyclone II)

6 Background (Source of Variation) Nassif (1998) –Environmental factors Power supply voltage Ambient temperature –Physical factors Wafer-level variations –Smooth variations that occur across a wafer Die-level variation –Imperfect masks –Lithography Wafer-die interactions –Location of die on wafer Random residuals –Random

7 Why Bother? Cheng et al –Statistical static timing analysis (SSTA) assumes all chips are physically identical –Ignores potential process variability –Statistics do not (necessarily) match real life –Process variations can make near-critical paths into critical paths

8 SSTA is No Substitute for the Real Thing Kassapaki et al –Create actual-delay circuits by using a dual-rail approach –Uses extra gates/LUTs/LEs (massive area penalty) –Delay measurement show 57.96% average inaccuracy compared to STA –Little difference over chips Turns out their process is very similar to speed binning (use of well known circuits and delay testing)

9 The Simulation Solution Srinivasan et al (2006) –Separate FPGA into regions –Characterize each region in terms of speed All characterizations done using SPICE simulations –Discard logic blocks that are below a certain speed –Place and route accordingly –Result: On average, FPGAs operate at 12% slower than the clock frequency due t variations

10 Measurements on Hardware Muhkerjee and Skadron (2006) –Measured process variation using ring oscillators on XUP Virtex II Pro –Only show results for approx. 40 tests –Found no distinguishable correlation between location on chip and speed of logic elements –Little in terms of conclusions

11 Plan of Action Determine best method of testing and recording data Acquire FPGAs Test Cyclone II FPGAs (-8 grade) –Build variation map for Cyclone IIs Determine intra-die variation –Determine inter-die variation (if more than one is acquired) Test Stratix II (-5 grade) –Build variation map Develop optimized (?) layout based on variation map –Compare speed of test circuit using variation aware placement versus generic place and route tools