1 Register-Transfer Level (RTL) Design Recall –Chapter 2: Combinational Logic Design First step: Capture behavior (using equation or truth table) Remaining.

Slides:



Advertisements
Similar presentations
CPE 201 Digital Design Lecture 25: Register Transfer Level Design (2)
Advertisements

CS1Q Computer Systems Lecture 12 Simon Gay. Lecture 12CS1Q Computer Systems - Simon Gay 2 Design of Sequential Circuits The systematic design of sequential.
Lecture 23: Registers and Counters (2)
Registers and Counters
TOPIC : Finite State Machine(FSM) and Flow Tables UNIT 1 : Modeling Module 1.4 : Modeling Sequential circuits.
1 Introduction Sequential circuit –Output depends not just on present inputs (as in combinational circuit), but on past sequence of inputs Stores bits,
Digital Design - Sequential Logic Design Chapter 3 - Sequential Logic Design.
Flip-Flops, Registers, Counters, and a Simple Processor
Sequential Circuits1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.
FLOWCHART BASED DESIGN A flowchart is ideal for a process that has sequential process steps. The steps will be executed in a simple order that may change.
Sequential Logic Design Process A sequential circuit that controls Boolean outputs and a specific time- ordered behavior is called a controller. StepDescription.
Register-Transfer Level (RTL) Design
Chapter 9: Hardware Description Languages
Digital Design Copyright © 2006 Frank Vahid 1 a b F InputsOutput a'b'a' b Converting among Representations Can convert from any representation.
Give qualifications of instructors: DAP
Basic Register Typically, we store multi-bit items
1 Lecture 14: FSM and Basic CPU Design Today’s topics:  Finite state machines  Single-cycle CPU Reminder: midterm on Tue 10/24  will cover Chapters.
1 Introduction Chapters 2 & 3: Introduced increasingly complex digital building blocks –Gates, multiplexors, decoders, basic registers, and controllers.
Controller Design Five step controller design process.
Register-Transfer Level (RTL) Design The combination of a controller and datapath is known as a processor. The most common method of designing a processor.
Chapter 11: System Design Methodology Digital System Designs and Practices Using Verilog HDL and 2008, John Wiley11-1 Ders 9: RTL Design.
Chapter 9: Hardware Description Languages
Digital Design – Register-Transfer Level (RTL) Design Chapter 5 - Register-Transfer Level (RTL) Design.
Sequential Circuit  It is a type of logic circuit whose output depends not only on the present value of its input signals but on the past history of its.

1 COMP541 State Machines Montek Singh Feb 8, 2012.
Elevator Controller We’re hired to design a digital elevator controller for a four-floor building st try: Design a counter that counts up.
1 4-Integrating Peripherals in Embedded Systems. 2 Introduction Single-purpose processors  Performs specific computation task  Custom single-purpose.
ECE 101 An Introduction to Information Technology Digital Logic.
Rabie A. Ramadan Lecture 3
Introduction to Computer Engineering ECE/CS 252, Fall 2010 Prof. Mikko Lipasti Department of Electrical and Computer Engineering University of Wisconsin.
Introduction to Sequential Logic Design Finite State-Machine Design.
Introduction to State Machine
Digital Design – Hardware Description Languages Chapter 9 - Hardware Description Languages.
Computer Organization & Programming Chapter 5 Synchronous Components.
Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Complete Example.
CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Latches & Flip-Flops.
Instructor: Alexander Stoytchev
DLD Lecture 26 Finite State Machine Design Procedure.
Hardware Description Languages Digital Logic Design Instructor: Kasım Sinan YILDIRIM.
Digital Design 2e Copyright © 2010 Frank Vahid 1 How To Capture Desired Behavior as FSM List states –Give meaningful names, show initial state –Optionally.
Lecture 21: Registers and Counters (1)
ECE 274 Digital Logic RTL Design using Verilog Verilog for Digital Design Ch. 5.
Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Transistor: Building.
1 ENGG 1015 Tutorial Three Examples of Finite State Machines Supplementary notes Learning Objectives  Learn about Design of Finite State Machines Ack.:
1 COMP541 Finite State Machines - 1 Montek Singh Sep 22, 2014.
Digital Design 2e Copyright © 2010 Frank Vahid 1 RTL Design Process: Create a datapath Sub-steps –HLSM data inputs/outputs  Datapath inputs/outputs. –HLSM.
Instructor: Alexander Stoytchev CprE 281: Digital Logic.
REGISTER TRANSFER LANGUAGE (RTL) INTRODUCTION TO REGISTER Registers1.
Finite State Machine. Clock Clock cycle Sequential circuit Digital logic systems can be classified as combinational or sequential. – Combinational circuits.
1 COMP541 Sequential Logic – 2: Finite State Machines Montek Singh Feb 29, 2016.
Digital Logic Structures: Chapter 3 COMP 2610 Dr. James Money COMP
1 Lecture 13: Sequential Circuits, FSM Today’s topics:  Sequential circuits  Finite state machines  Single-cycle CPU Reminder: midterm on Tue 10/20.
Digital Design - Sequential Logic Design
REGISTER TRANSFER LANGUAGE (RTL)
Instructor: Alexander Stoytchev
Dr. Clincy Professor of CS
Overview Instruction Codes Computer Registers Computer Instructions
Instructor: Alexander Stoytchev
Jeremy R. Johnson Mon. Apr. 3, 2000
ECE 434 Advanced Digital System L13
Lecture 13: Sequential Circuits, FSM
Introduction to Sequential Circuits
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
Register-Transfer Level Components in Verilog
ECE 352 Digital System Fundamentals
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
Learning Outcome By the end of this chapter, students are expected to understand the principle of RTL design.
ECE 352 Digital System Fundamentals
Finite State Machine Continued
Presentation transcript:

1 Register-Transfer Level (RTL) Design Recall –Chapter 2: Combinational Logic Design First step: Capture behavior (using equation or truth table) Remaining steps: Convert to circuit –Chapter 3: Sequential Logic Design First step: Capture behavior (using FSM) Remaining steps: Convert to circuit RTL Design (the method for creating custom processors) –First step: Capture behavior (using high- level state machine, to be introduced) –Remaining steps: Convert to circuit Capture behavior Convert to circuit

2 RTL Design Method

3 Step 1: Laser-Based Distance Measurer Example of how to create a high-level state machine to describe desired processor behavior Laser-based distance measurement – pulse laser, measure time T to sense reflection –Laser light travels at speed of light, 3*10 8 m/sec –Distance is thus D = T sec * 3*10 8 m/sec / 2 Object of interest D 2D = T sec * 3*10 8 m/sec sensor laser T (in seconds)

4 Step 1: Laser-Based Distance Measurer Inputs/outputs –B: bit input, from button to begin measurement –L: bit output, activates laser –S: bit input, senses laser reflection –D: 16-bit output, displays computed distance sensor laser T (in seconds) Laser-based distance measurer 16 from button to display S L D B to laser from sensor

5 Step 1: Laser-Based Distance Measurer Step 1: Create high-level state machine Begin by declaring inputs and outputs Create initial state, name it S0 –Initialize laser to off (L=0) –Initialize displayed distance to 0 (D=0) Laser- based distance measurer 16 from button to display S L D B to laser from sensor Inputs:B, S(1 bit each) Outputs:L (bit), D (16 bits) S0 ? L = 0 (laser off) D = 0 (distance = 0) a

6 Step 1: Laser-Based Distance Measurer Add another state, call S1, that waits for a button press –B’ – stay in S1, keep waiting –B – go to a new state S2 Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits) S0 L = 0 D = 0 S1 ? B’ (button not pressed) B (button pressed) S0 Q: What should S2 do?A: Turn on the laser a a Laser- based distance measurer 16 from button to display S L D B to laser from sensor

7 Step 1: Laser-Based Distance Measurer Add a state S2 that turns on the laser (L=1) Then turn off laser (L=0) in a state S3 S0S1S2 L = 0 D = 0 L = 1 (laser on) S3 L = 0 (laser off) B’ B a Q: What do next?A: Start timer, wait to sense reflection a Laser- based distance measurer 16 from button to display S L D B to laser from sensor Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits)

8 Step 1: Laser-Based Distance Measurer Stay in S3 until sense reflection (S) To measure time, count cycles for which we are in S3 –To count, declare local register Dctr –Increment Dctr each cycle in S3 –Initialize Dctr to 0 in S1. S2 would have been O.K. too Laser-based distance measurer 16 from button to display S L D B to laser from sensor Local Registers: Dctr (16 bits) S0S1S2S3 L = 0 D = 0 L = 1L = 0 Dctr = Dctr + 1 (count cycles) Dctr = 0 (reset cycle count) B’ B S’ (no reflection) S (reflection) ? a Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits)

9 Step 1: Laser-Based Distance Measurer Once reflection detected (S), go to new state S4 –Calculate distance –Assuming clock frequency is 3x10 8, Dctr holds number of meters, so D=Dctr/2 After S4, go back to S1 to wait for button again Laser-based distance measurer 16 from button to display S L D B to laser from sensor S0S1S2S3 L = 0 D = 0 L = 1L=0 Dctr = Dctr + 1 Dctr = 0 B’ S’ BS D = Dctr / 2 (calculate D) S4 a Local Registers: Dctr (16 bits) Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits)

10 Step 2: Create a Datapath Datapath must –Implement data storage –Implement data computations Look at high-level state machine, do three substeps –(a) Make data inputs/outputs be datapath inputs/outputs –(b) Instantiate declared registers into the datapath (also instantiate a register for each data output) –(c) Examine every state and transition, and instantiate datapath components and connections to implement any data computations Instantiate: to introduce a new component into a design.

11 Step 2: Laser-Based Distance Measurer (a) Make data inputs/outputs be datapath inputs/outputs (b) Instantiate declared registers into the datapath (also instantiate a register for each data output) (c) Examine every state and transition, and instantiate datapath components and connections to implement any data computations Datapath Dreg_clr Dctr_clr Dctr_cnt Dreg_ld Local Registers: Dctr (16 bits) S0S1S2S3 L = 0 D = 0 L = 1L=0 Dctr = Dctr + 1 Dctr = 0 B ‘ S ‘ BS D = Dctr / 2 (calculate D) S4 load Q I Dreg: 16-bit register Q Dctr: 16-bit up-counter 16 D clear count a Inputs: B, S (1 bit each)Outputs: L (bit), D (16 bits)

12 Step 2: Laser-Based Distance Measurer (c) (continued) Examine every state and transition, and instantiate datapath components and connections to implement any data computations clear count clear load QQ I Dctr: 16-bit up-counter Dreg: 16-bit register 16 D Datapath Dreg_clr Dctr_clr Dctr_cnt Dreg_ld 16 >>1 a Local Registers: Dctr (16 bits) S0S1S2S3 L = 0 D = 0 L = 1L=0 Dctr = Dctr + 1 Dctr = 0 B ‘ S ‘ BS D = Dctr / 2 (calculate D) S4 Inputs: B, S (1 bit each)Outputs: L (bit), D (16 bits)

13 Step 3: Connecting the Datapath to a Controller Laser-based distance measurer example Easy – just connect all control signals between controller and datapath 300 MHz Clock D B L S 16 to display from button Controller to laser from sensor Datapath Dreg_clr Dreg_ld Dctr_clr Dctr_cnt clear count clear load Q Q I Dctr: 16-bit up-counter Dreg: 16-bit register 16 D Datapath Dreg_clr Dctr_clr Dctr_cnt Dreg_ld 16 >>1

14 Step 4: Deriving the Controller’s FSM FSM has same structure as high- level state machine –Inputs/outputs all bits now –Replace data operations by bit operations using datapath 300 MHz Clock D B L S 16 to display from button Controller to laser f rom sensor Datapath Dreg_clr Dreg_ld Dctr_clr Dctr_cnt Inputs: B, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt S0S1S2S3 L = 0L = 1L = 0 B’ S’ BS S4 L = 0 Inputs: B, S (1 bit each)Outputs: L (bit), D (16 bits) Local Registers: Dctr (16 bits) S0S1S2S3 L = 0 D = 0 L = 1L=0 Dctr = Dctr + 1 Dctr = 0 B’ S’ BS D = Dctr / 2 (calculate D) S4 a Dreg_clr = 1 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 0 (laser off) (clear D reg) Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 1 Dctr_cnt = 0 (clear count) Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 0 (laser on) Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 1 (laser off) (count up) Dreg_clr = 0 Dreg_ld = 1 Dctr_clr = 0 Dctr_cnt = 0 (load D reg with Dctr/2) (stop counting)

15 Step 4: Deriving the Controller’s FSM Using shorthand of outputs not assigned implicitly assigned 0 a S0S1S2S3 L = 0L = 1L = 0 B’ S’ BS S4 L = 0 Dreg_clr = 1 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 0 (laser off) (clear D reg) Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 1 Dctr_cnt = 0 (clear count) Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 0 (laser on) Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 1 (laser off) (count up) Dreg_clr = 0 Dreg_ld = 1 Dctr_clr = 0 Dctr_cnt = 0 (load D reg with Dctr/2) (stop counting) S0S1S2S3 L = 0L = 1L = 0 B’S’ BS (laser on) S4 Inputs: B, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt Dreg_clr = 1 (laser off) (clear D reg) Dctr_clr = 1 (clear count) Dctr_cnt = 1 (laser off) (count up) Dreg_ld = 1 Dctr_cnt = 0 (load D reg with Dctr/2) (stop counting)

16 Step 4 Implement FSM as state register and logic (Ch3) to complete the design clear count clear load QQ I Dctr: 16-bit up-counter Dreg: 16-bit register 16 D Datapath Dreg_clr Dctr_clr Dctr_cnt Dreg_ld 300 MHz Clock D B L S 16 to display from button Controller to laser from sensor Datapath Dreg_clr S0S1S2S3 L = 0L = 1L = 0 B’S’ BS (laser on) S4 Inputs: B, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt Dreg_clr = 1 (laser off) (clear D reg) Dctr_clr = 1 (clear count) Dctr_cnt = 1 (laser off) (count up) Dreg_ld = 1 Dctr_cnt = 0 (load D reg with Dctr/2) (stop counting) Dreg_ld Dctr_clr Dctr_cnt 16 >>1