The Assembly Process Basically how does it all work.

Slides:



Advertisements
Similar presentations
1 Lecture 3: MIPS Instruction Set Today’s topic:  More MIPS instructions  Procedure call/return Reminder: Assignment 1 is on the class web-page (due.
Advertisements

Branches Two branch instructions:
MIPS ISA-II: Procedure Calls & Program Assembly. (2) Module Outline Review ISA and understand instruction encodings Arithmetic and Logical Instructions.
MIPS ISA-II: Procedure Calls & Program Assembly. (2) Module Outline Review ISA and understand instruction encodings Arithmetic and Logical Instructions.
1 Procedure Calls, Linking & Launching Applications Lecture 15 Digital Design and Computer Architecture Harris & Harris Morgan Kaufmann / Elsevier, 2007.
1 Lecture 4: Procedure Calls Today’s topics:  Procedure calls  Large constants  The compilation process Reminder: Assignment 1 is due on Thursday.
Statement Format MIPS assembly language statements have the following format label: opcode operand,operand,operand # comment Label identifies the statement.
The University of Adelaide, School of Computer Science
Assembly Language Working with the CPU.
Lecture 8: MIPS Instruction Set
CS61C L11 Linker © UC Regents 1 CS61C - Machine Structures Lecture 11 - Starting a Program October 4, 2000 David Patterson
Lec 9Systems Architecture1 Systems Architecture Lecture 9: Assemblers, Linkers, and Loaders Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some.
Assembly Process. Machine Code Generation Assembling a program entails translating the assembly language into binary machine code This requires more than.
 Procedures (subroutines) allow the programmer to structure programs making them : › easier to understand and debug and › allowing code to be reused.
Comp Sci instruction encoding 1 Instruction Encoding MIPS machine language Binary encoding of instructions MIPS instruction = 32 bits Three instruction.
ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 4: Arithmetic / Data Transfer Instructions Partially adapted from Computer Organization.
Instruction Representation II (1) Fall 2007 Lecture 10: Instruction Representation II.
MIPS Assembler Programming
RISC Concepts, MIPS ISA and the Mini–MIPS project
Lecture 5 Sept 14 Goals: Chapter 2 continued MIPS assembly language instruction formats translating c into MIPS - examples.
CS 61C L14Introduction to MIPS: Instruction Representation II (1) Garcia, Spring 2004 © UCB Roy Wang inst.eecs.berkeley.edu/~cs61c-tf inst.eecs.berkeley.edu/~cs61c.
ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 6: Logic/Shift Instructions Partially adapted from Computer Organization and Design, 4.
COMPUTER ARCHITECTURE & OPERATIONS I Instructor: Hao Ji.
CMPE12c Homework #4 Spring 2003 Use the MAL/TAL sheets passed out during the exam 1) (15 pts) Write a MAL code procedure that calculates the factorial.
9/29: Lecture Topics Memory –Addressing (naming) –Address space sizing Data transfer instructions –load/store on arrays on arrays with variable indices.
Computer Architecture and Design – ECEN 350 Part 4 [Some slides adapted from M. Irwin, D. Paterson and others]
IT253: Computer Organization Lecture 5: Assembly Language and an Introduction to MIPS Tonga Institute of Higher Education.
Computer Organization and Design Instruction Sets Montek Singh Wed, Sep 12, 2012 Lecture 5.
CSE378 Instr. encoding.1 Instruction encoding The ISA defines –The format of an instruction (syntax) –The meaning of the instruction (semantics) Format.
In Class Execise. .data A:.word 0,1,2,3,4,5,6,7,8,9.text.globl main main: la $a0,A li $a1,6 li $a2,5 jal onUpStream done: li $v0, 10# exit syscall onUpStream:
Chapter 10 The Assembly Process. What Assemblers Do Translates assembly language into machine code. Assigns addresses to all symbolic labels (variables.
1 CS/COE0447 Computer Organization & Assembly Language Chapter 2 Part 4.
April 23, 2001Systems Architecture I1 Systems Architecture I (CS ) Lecture 9: Assemblers, Linkers, and Loaders * Jeremy R. Johnson Mon. April 23,
Informationsteknologi Friday, September 28, 2007Computer Architecture I - Class 21 Today’s class More assembly language programming.
Lecture 4: MIPS Instruction Set
True Assembly Language Part I. The Assembly Process The process of translating a MAL code (an assembly language program) into machine code (a sequence.
CMPE 325 Computer Architecture II
9/29: Lecture Topics Conditional branch instructions
Csci 136 Computer Architecture II – More on MIPS ISA Xiuzhen Cheng
MIPS Assembly Language Chapter 13 S. Dandamudi To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer,
CENG 311 Starting a Program. Review (1/2) °IEEE 754 Floating Point Standard: Kahan pack as much in as could get away with +/- infinity, Not-a-Number (Nan),
The Assembly Process Basically why does it all work.
MIPS Assembly Language Chapter 15 S. Dandamudi To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.
The Assembly Process Computer Organization and Assembly Language: Module 10.
Computer Architecture & Operations I
Lecture 6: Assembly Programs
Computer Architecture Instruction Set Architecture
Computer Organization and Design Instruction Sets - 2
MIPS Coding Continued.
Computer Organization and Design Instruction Sets - 2
RISC Concepts, MIPS ISA Logic Design Tutorial 8.
Computer Organization and Design Instruction Sets
MPIS Instructions Functionalities of instructions Instruction format
MIPS Instruction Encoding
ECE232: Hardware Organization and Design
Computer Organization and Design Assembly & Simulation
MIPS Instruction Encoding
Instruction encoding The ISA defines Format = Encoding
Flow of Control -- Conditional branch instructions
UCSD ECE 111 Prof. Farinaz Koushanfar Fall 2018
MIPS Assembly.
Flow of Control -- Conditional branch instructions
MIPS Coding Continued.
CS352H Computer Systems Architecture
Generalities for Assembly Language
Adventures in Assembly Land
Program Assembly.
Adventures in Assembly Land
9/27: Lecture Topics Memory Data transfer instructions
MIPS Arithmetic and Logic Instructions
Presentation transcript:

The Assembly Process Basically how does it all work

CMPE12cCyrus Bazeghi 2 A computer understands machine code - binary People (and compilers) write assembly language Assembler Assembly code Machine code The Assembly Process

CMPE12cCyrus Bazeghi 3 The Assembly Process An assembler is a program that translates each instruction to its binary machine code equivalent. It is a relatively simple program There is a one-to-one or near one-to-one correspondence between assembly language instructions and machine language instructions. Assemblers do some code manipulation Like MAL to TAL Label resolution A “macro assembler” can process simple macros like puts, or preprocessor directives.

CMPE12cCyrus Bazeghi 4 MAL  TAL MAL is the set of instructions accepted by the assembler. TAL is a subset of MAL – the instructions that can be directly turned into machine code. There are many MAL instructions that have no single TAL equivalent. To determine whether an instruction is a TAL instruction or not: Look in appendix C or on the MAL/TAL sheet. The assembler takes (non MIPS) MAL instructions and synthesizes them into 1 or more MIPS instructions.

CMPE12cCyrus Bazeghi 5 MAL  TAL mul $8, $17, $20 For example Becomes MIPS has 2 registers for results from integer multiplication and division: HI and LO Each is a 32 bit register mult and multu places the least significant 32 bits of its result into LO, and the most significant into HI. Multiplying two 32-bit numbers gives a 64-bit result (2 32 – 1)(2 32 – 1) = 2 64 – 2x mult $17, $20 mflo $8

CMPE12cCyrus Bazeghi 6 MAL  TAL mflo, mtlo, mfhi, mthi Move From loMove To hi Data is moved into or out of register HI or LO One operand is needed to tell where the data is coming from or going to. For division (div or divu) HI gets the remainder LO gets the dividend Why aren’t these just put in $0-$31 directly?

CMPE12cCyrus Bazeghi 7 MAL  TAL TAL has only base displacement addressing So this: lw $8, label Becomes: la $7, label lw $8, 0($7) Which becomes lui $8, 0xMSPART of label ori $8, $8, 0xLSpart of label lw $8, 0($8)

CMPE12cCyrus Bazeghi 8 MAL  TAL Instructions with immediate values are synthesized with other instructions So:add $sp, $sp, 4 Becomes:addi $sp, $sp, 4 For TAL: add requires 3 operands in registers. addi requires 2 operands in registers and one operand that is an immediate. In MIPS assembly immediate instructions include: addi, addiu, andi, lui, ori, xori Why not more?

CMPE12cCyrus Bazeghi 9 MAL  TAL TAL implementation of I/O instructions This: putc $18# if you got to use macros Becomes: addi$2, $0, 11# code for putc add$4, $18, $0# put character argument in $4 syscall# ask operating system to do a function

CMPE12cCyrus Bazeghi 10 MAL  TAL getc$11 Becomes: addi$2, $0, 12 syscall add$11, $0, $2 puts$13 Becomes: addi$2, $0, 4 add$4, $0, $13 syscall done Becomes: addi$2, $0, 10 syscall

CMPE12cCyrus Bazeghi 11 MAL  TAL MALTAL Arithmetic Instructions: move $4, $3add $4, $3, $0 add $4, $3, 15addi $4, $3, 15 # also andi, ori,.. mul $8, $9, $10mult $9, $10 #HI || LO  product # never overflow mflo $8 # $8  $L0, ignore $HI! div $8, $9, $10div $9, $10 # $LO  quotient # $HI  remainder mflo $8 rem $8, $9, $10div $9, $10 mfhi $8

CMPE12cCyrus Bazeghi 12 MAL  TAL MALTAL Branch Instructions: bltz, bgez, blez, bgtz, beqz, bnez, blt, bge, bgt, beq, bne bltz, bgez, blez, bgtz, beq, bne beqz $4, loopbeq $4, $0, loop blt $4, $5, targetslt $t0, $4, $5 # $t0 is 1 if $4 < $5 # $t0 is 0 otherwise bne $t0, $0, target

CMPE12cCyrus Bazeghi 13 Assembler The assembler will: Assign addresses Generate machine code If necessary, the assembler will: Translate (synthesize) from the accepted assembly to the instructions available in the architecture Provide macros and other features Generate an image of what memory must look like for the program to be executed.

CMPE12cCyrus Bazeghi 14 Assembler What should the assembler do when it sees a directive?.data.text.space,.word,.byte,.float main: How is the memory image formed?

CMPE12cCyrus Bazeghi 15 Assembler Example Data Declaration Assembler aligns data to word addresses unless told not to. Assembly process is very sequential..data a1:.word 3 a2:.byte ‘\n’ a3:.space 5 AddressContents 0x x x x??????0a 0x x???????? 0x c0x????????

CMPE12cCyrus Bazeghi 16 Machine code generation opcode is 6 bits – addi is defined to be rs – source register is 5 bits, encoding of 20, rt – target register is 5 bits, encoding of 8, The 32-bit instruction for addi $8, $20, 15 is: Or 0x f Assembly language:addi $8, $20, 15 opcode rtrs immediate 310 opcodersrtimmediate Machine code format:

CMPE12cCyrus Bazeghi 17 Instruction Formats I-Type Instructions with 16-bit immediates ADDI, ORI, ANDI, … LW, SW BNE OPC:6rs1:5rd:5immediate:16 OPC:6rs1:5rs2/rddisplacement:16 OPC:6rs1:5rs2:5distance(instr):16

CMPE12cCyrus Bazeghi 18 Instruction Formats J-Type Instructions with 26-bit immediate J, JAL R-Type All other instructions ADD, AND, OR, JR, JALR, SYSCALL, MULT, MFHI, LUI, SLT OPC:626-bits of jump address OPC:6rs1:5rs2:5ALU function:11rd:5

CMPE12cCyrus Bazeghi 19 Assembly Example.data a1:.word3 a2:.word16:4 a3:.word5.text main: la $6, a2 loop:lw $7, 4($6) mul $8, $9, $10 b loop done “Symbol Table” SymbolAddress a a a main loop

CMPE12cCyrus Bazeghi 20 Assembly Example addressContents (hex)Contents (binary) c Memory map of.data section

CMPE12cCyrus Bazeghi 21 Assembly Example Translation of MAL to TAL code.text main:lui $6, 0x0040# la $6, a2 ori $6, $6, 0x0004 loop:lw $7, 4($6) mult $9, $10# mul $8, $9, $10 mflo $8 beq $0, $0, loop# b loop ori $2, $0, 10# done syscall

CMPE12cCyrus Bazeghi 22 addressContents (hex) Contents (binary) c (lui) c (ori) cc (lw) c012a (mult) (mflo) fffc (beq) a (ori) C c (sys) Memory map of.text section Assembly Example

CMPE12cCyrus Bazeghi 23 At execution time: PC  NPC + {sign extended offset field,00} PC points to instruction after the beq when offset is added. At assembly time: Byte offset= target addr – (address of branch + 4) = – ( ) = FFFFFFF4 (-12) Branch offset computation Assembly Example

CMPE12cCyrus Bazeghi 24 4 important observations: Offset is stored in the instruction as a word offset An offset may be negative The field dedicated to the offset is 16 bits, range is thus limited More simply: Just count the number of instructions from instruction following branch to target, encode that as a 16-bit value Assembly Example

CMPE12cCyrus Bazeghi 25 Assembly At execution time: PC  {most significant 4 bits of PC, target field, 00} At assembly time: Take 32 bit target address Eliminate least significant 2 bits (since word aligned) Eliminate most significant 4 bits What remains is 26 bits, and goes in the target field Jump target computation

CMPE12cCyrus Bazeghi 26 Linking N’ Loading The process of building/configuring the executable, placing it in memory, and running it.

CMPE12cCyrus Bazeghi 27 Linking and Loading Searches libraries Reads object files Relocates code/data Resolves external references Creates object file Linker

CMPE12cCyrus Bazeghi 28 Creates address spaces for text & data Copies text & data in memory Initializes stack and copy args Initializes regs (maybe) Initializes other things (OS) Jumps to startup routine –And then to address of “main:” Loader Linking and Loading

CMPE12cCyrus Bazeghi 29 Object file Linking and Loading Section:Description: HeaderStart/size of other parts TextMachine Language DataStatic data – size and initial values Relocation infoInstructions and data with absolute addresses Symbol tableAddresses of external labels Debuggin` infoBreak points

CMPE12cCyrus Bazeghi 30 Linking and Loading The data section starts at 0x for the MIPS processor. If the source code has,.data a1:.word 15 a2:.word –2 then the assembler specifies initial configuration memory as address:contents: 0x x Like the data, the code needs to be placed starting at a specific location to make it work

CMPE12cCyrus Bazeghi 31 Linking and Loading Consider the case where the assembly language code is split across 2 files. Each is assembled separately. File 1:.data a1:.word 15 a2:.word –2.text main:la $t0, a1 add $t1, $t0, $s3 jal proc5 done.data a3:.word 0.text proc5:lw $t6, a1 sub $t2, $t0, $s4 jr $ra File2:

CMPE12cCyrus Bazeghi 32 Linking and Loading What happens to… a1 a3 main proc5 lw la jal

CMPE12cCyrus Bazeghi 33 Linking and Loading Problem: there are absolute addresses in the machine code. Solutions: 1.Only allow a single source file Why not? 2.Allow linking and loading to Relocate pieces of data and code sections Finish the machine code where symbols were left undefined Basically makes absolute address a relative address

CMPE12cCyrus Bazeghi 34 Linking and Loading The assembler will: Start both data and code sections at address 0, for all files. Keep track of the size of every data and code section. Keep track of all absolute addresses within the file.

CMPE12cCyrus Bazeghi 35 Linking and loading will: Assign starting addresses for all data and code sections, based on their sizes. The blocks of data and code go at non- overlapping locations. Fix all absolute addresses in the code Place the linked code and data in memory at the location assigned Start it up Linking and Loading

CMPE12cCyrus Bazeghi 36 MIPS Example Code levels of abstraction (from James Larus) “C” code #include int main (int argc, char *argv[]) { int I; int sum = 0; for (I=0; I<=100; I++) sum += I * I; printf (“The sum =%d\n”,sum); } Compile this HLL into a machine’s assembly language with the compiler.

CMPE12cCyrus Bazeghi 37 MIPS Example.text main: subu$sp, 32 sw$31, 20($sp) sw$4, 32($sp) sw$0, 24($sp) sw$0, 28($sp) loop: lw$14, 28($sp) mul$15, $14, $14 lw$24, 24($sp) addu$25, $24, $15 sw$8, 28($sp) ble$8, 100, loop la$4, str lw$5, 24($sp) jalprintf move$2, $0 lw$31, 20($sp) addu$sp, 32 jr$31.data str:.asciiz “The sum =%d\n” Converted into MAL…

CMPE12cCyrus Bazeghi 38 addiu$sp, $sp,-32 sw$ra, 20($sp) sw$a0, 32($sp) sw$a1, 36($sp) sw$0, 24($sp) sw$0, 28($sp) lwt6, 28($sp) lw$t8, 24($sp) multu$t6, $t6 addiu$t0, $t6, 1 slti$at, $t0, 101 sw$t0, 28($sp) mflo$t7 addu$t9, $t8, $t7 bne$at, $0, -9 sw$t9, 24($sp) lui$a0,4096 lw$a1, 24($sp) jal addiu$a0, $a0, 1072 lw$ra, 20($sp) addiu$sp, $sp, 32 jr$ra Which the assembler then translates into binary machine code for instructions and data. Now resolve the labels and convert to MIPS… MIPS Example

CMPE12cCyrus Bazeghi 39 Real MIPS Machine language MIPS Example