Department of Electrical and Computer Engineering System-Level Simulation for Continuous-Time Delta-Sigma Modulator in MATLAB SIMULINK MATTHEW WEBB, HUA TANG Department of Electrical and Computer Engineering University of Minnesota Duluth Duluth, MN, 55812, USA

Department of Electrical and Computer Engineering Background Ample work on circuit-level design Relatively less on system-level design –Earliest work on discrete-time(DT) ∆∑M –More recently on continuous-time(CT) ∆∑M None have the simplicity, adaptability, and visualization of MATLAB SIMULINK

Department of Electrical and Computer Engineering Outline Problem Formulation Core non-idealities Modeling solutions Final results Conclusion

Department of Electrical and Computer Engineering Problem Formulation Building blocks of CT ∆∑M –Operational transconductance amplifiers –Operational amplifiers –Comparator –Current feedback blocks Performance of ∆∑M is dependent on the non-idealities of the components

Department of Electrical and Computer Engineering CT ∆∑M

Department of Electrical and Computer Engineering Addressed Non-Idealities Clock jitter at the comparator Operational amplifier noise Integrator leakage due to finite gain Amplifier finite bandwidth (BW) Amplifier slew rate (SR) Amplifier saturation Transconductor nonlinearity

Department of Electrical and Computer Engineering Clock Jitter Temporal variation of clock period Results in non-uniform sampling Zero mean random variable Modeled with a normal distribution MATLAB function randn

Department of Electrical and Computer Engineering Clock Jitter Plot T = 6.51nsec

Department of Electrical and Computer Engineering Noise Most important source is the intrinsic noise of the amplifier Modeled using a random number generator to create additive white noise Only necessary to model at first stage

Department of Electrical and Computer Engineering Noise Plot MaxNoise = 1mV

Department of Electrical and Computer Engineering Integrator Many important non-idealities Similar to DT modeling with a few distinct differences

Department of Electrical and Computer Engineering Finite DC Gain Not infinite due to circuit constraints Causes leaky integration Modeled by subtracting a fraction of the integrator output from the integrator input Insignificant when compared to other non- idealities

Department of Electrical and Computer Engineering Slew Rate and Finite Bandwidth Slew rate affects nonlinear settling time Finite BW affects linear setting time More likely to be limited by slew rate Different from DT because integration occurs over the entire sampling period Important to model at all stages

Department of Electrical and Computer Engineering Saturation Important to model as it affects the dynamic of signals Since the modulator is scaled, this effect was observed to rarely, if ever, happen So also insignificant in most cases

Department of Electrical and Computer Engineering Nonlinearity Nonlinearity increases harmonics, which decreases overall SNR Nonlinearity of OTA is main concern Not modeled in DT version No even order harmonics if fully differential Third order most significant Only necessary to model at first stage

Department of Electrical and Computer Engineering Nonlinearity Plot

Department of Electrical and Computer Engineering Final Model

Department of Electrical and Computer Engineering Parameters for Complete Simulation Non-idealityValue P-p jitter7.25 psec RMS noise10 μV Nonlinear coeff (84dB THD) Finite gain5000 Finite BW300 MHz Slew rate100 V/μsec Saturation± 1.25

Department of Electrical and Computer Engineering Final Results Plot

Department of Electrical and Computer Engineering Conclusions System-level simulation is a great benefit before circuit-level simulation Can use block specifications obtained from system-level simulation as inputs to circuit- level design Extremely efficient, computing complete dynamic range plots in less than one hour

Department of Electrical and Computer Engineering Questions?